{"id":30031,"date":"2019-10-31T21:33:20","date_gmt":"2019-10-31T18:33:20","guid":{"rendered":"https:\/\/prohoster.info\/blog\/linux-foundation-zajmetsya-open-source-chipami\/"},"modified":"2019-10-31T21:33:20","modified_gmt":"2019-10-31T18:33:20","slug":"linux-foundation-zajmetsya-open-source-chipami","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/linux-foundation-zajmetsya-open-source-chipami","title":{"rendered":"Linux Foundation will handle open source chips","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

The Linux Foundation has launched a new initiative \u2014 CHIPS Alliance. As part of this project, the organization will develop an open-source RISC-V command system and technologies for creating processors based on it. Let's take a closer look at what's happening in this area.<\/p>\n

\"Linux<\/a><\/noindex><\/a><\/noindex>
\n\/ \u0444\u043e\u0442\u043e Gareth Halfacree<\/a><\/noindex> CC BY-SA<\/a><\/noindex><\/i><\/p>\n

Why CHIPS Alliance Was Established<\/h2>\n

\nPatches protecting against Meltdown and Spectre sometimes reduce server performance<\/a><\/noindex> by up to 50%. At the same time, new variants of vulnerabilities related to speculative execution continue to emerge. One of them became known in early March<\/a><\/noindex> \u2014 cybersecurity experts dubbed it Spoiler. This situation affects the sparked<\/a><\/noindex> need to reassess existing hardware solutions and approaches to their development. In particular, Intel is already preparing<\/a><\/noindex> a new architecture for its processors that is immune to Meltdown and Spectre.<\/p>\n

The Linux Foundation has also joined the effort. The organization has launched its own initiative\u2014CHIPS Alliance\u2014whose participants will focus on developing processors based on RISC-V.<\/p>\n

What Projects Are Already Being Developed<\/h2>\n

<\/p>\n

The list of CHIPS Alliance participants includes Google, Western Digital (WD), and SiFive. Each of them has introduced their own developments. Let's discuss some of them.<\/p><\/blockquote>\n

<\/p>\n

RISCV-DV<\/h5>\n

\nThe search giant has released an open-source platform for testing processors based on RISC-V. The solution randomly generates<\/a><\/noindex> commands that allow<\/a><\/noindex> test the functionality of the device: it tests transition processes, the call stack, CSR<\/a><\/noindex>-registers, and more.<\/p>\n

For example, This is what the class looks like<\/a><\/noindex>, responsible for conducting a simple arithmetic instruction test:<\/p>\n

class riscv_arithmetic_basic_test extends riscv_instr_base_test;\n\n  `uvm_component_utils(riscv_arithmetic_basic_test)\n  `uvm_component_new\n\n  virtual function void randomize_cfg();\n    cfg.instr_cnt = 10000;\n    cfg.num_of_sub_program = 0;\n    cfg.no_fence = 1;\n    cfg.no_data_page = 1'b1;\n    cfg.no_branch_jump = 1'b1;\n    `DV_CHECK_RANDOMIZE_WITH_FATAL(cfg,\n                                   init_privileged_mode == MACHINE_MODE;\n                                   max_nested_loop == 0;)\n    `uvm_info(`gfn, $sformatf(\"riscv_instr_gen_config is randomized:n%0s\",\n                    cfg.sprint()), UVM_LOW)\n  endfunction\n\nendclass\n<\/code><\/pre>\n
\nAccording to words<\/a><\/noindex> For developers, the platform stands out from its counterparts by allowing thorough testing of all components of the chip, including the memory block.<\/p>\n
OmniXtend Protocol<\/h5>\n
\nThis is a network protocol from WD that ensures cache coherence when transferring data over Ethernet. OmniXtend<\/a><\/noindex> allows direct communication with the processor cache and is used to connect various accelerators: GPU or FPGA. It is also suitable for building multi-chip RISC-V based systems.<\/p>\n
The protocol is already supported by SweRV chips<\/a><\/noindex>, which are aimed at data processing in data centers. SweRV is a 32-bit dual-issue superscalar processor built using a 28-nanometer process technology. Each pipeline has nine stages, enabling multiple instructions to be loaded and executed simultaneously. The device operates at a frequency of 1.8 GHz.<\/p>\n
Rocket Chip generator<\/h5>\n
\nis a solution from SiFive, founded by the developers of RISC-V technology. Rocket Chip<\/a><\/noindex> is a generator of RISC-V processor cores in Chisel language. It is a<\/a><\/noindex> is a set of parameterized libraries used to create SoC<\/a><\/noindex>.<\/p>\n
As for Chisel<\/a><\/noindex>, which is a hardware description language based on Scala. It generates low-level Verilog code that is also suitable<\/a><\/noindex> is processed on ASICs and FPGAs. Thus, it enables the use of OOP principles in development RTL<\/a><\/noindex>.<\/p>\n
Prospects of the alliance<\/h2>\n
\nExperts say that the Linux Foundation initiative will make the processor market more democratic and open to new players. IDC noted note<\/a><\/noindex>, that the growing popularity of such projects will positively impact the development of machine learning technologies and AI systems as a whole.<\/p>\n
\"Linux
\n\/ \u0444\u043e\u0442\u043e Fritzchens Fritz<\/a><\/noindex> PD<\/i><\/p>\n
The development of open source processors will also lower the cost of designing custom chips. However, this will only occur if the Linux Foundation community can attract a sufficient number of developers.<\/p>\n
Similar projects<\/h2>\n
\nOther organizations are also developing projects related to open hardware. An example is the CXL consortium, which introduced the Compute Express Link standard in mid-March. This technology is analogous to OmniXtend and also connects CPU, GPU, and FPGA. The standard uses the PCIe 5.0 bus for data transfer.<\/p>\n
Another project focusing on processor technology development is MIPS Open, which emerged in December 2018. The initiative was created by the startup Wave Computing. The developers plan to open<\/a><\/noindex> access to the latest 32-bit and 64-bit MIPS instruction sets for the IT community. The project is set to launch it is anticipated<\/a><\/noindex> in the coming months.<\/p>\n
Overall, the open source approach is becoming widely accepted not only for software but also for hardware. Such projects are supported by major companies. Therefore, we can expect that in the near future, more devices based on open hardware standards will appear in the market.<\/p>\n
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