{"id":30161,"date":"2019-10-31T21:33:57","date_gmt":"2019-10-31T18:33:57","guid":{"rendered":"https:\/\/prohoster.info\/blog\/vyyasnilis-podrobnosti-ob-arhitekture-vstroennoj-grafiki-intel-11-go-pokoleniya\/"},"modified":"2019-10-31T21:33:57","modified_gmt":"2019-10-31T18:33:57","slug":"vyyasnilis-podrobnosti-ob-arhitekture-vstroennoj-grafiki-intel-11-go-pokoleniya","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/vyyasnilis-podrobnosti-ob-arhitekture-vstroennoj-grafiki-intel-11-go-pokoleniya","title":{"rendered":"Details have emerged about the architecture of Intel's 11th generation integrated graphics.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Yesterday, Intel showcased its new discrete graphics accelerator; however, no specifics were provided about it. In conjunction, TechPowerUp released new details about the architectural features of Intel's 11th generation integrated graphics (Gen11). Notably, this architecture, in a somewhat modified form, will also be utilized in Intel's discrete GPUs.<\/p>\n

\"Details
\n \"Details <\/p>\n

The published illustrations from Intel's technical documentation refer to the GT2 version of the 11th generation graphics. This class of integrated GPUs usually sees the most widespread use, as it is found in Intel Core S and U series desktop and mobile processors, targeting the mass market.<\/p>\n

\"Details <\/p>\n

According to the published information, Intel will continue to use its ring bus in Ice Lake processors, despite the increase in the number of cores. This is somewhat surprising since Intel has transitioned to a Mesh connection in its multi-core high-performance and server processors. Nevertheless, the general user will be offered a well-proven connection. Additionally, the new graphics architecture suggests that the integrated GPU will have priority access to the ring bus. For graphics, a bandwidth of 64 bytes per cycle is provided for both reading and writing, whereas each CPU core has only 32 bytes per cycle for reading and writing.<\/p>\n

\"Details <\/p>\n

Access to the Intel graphics memory will be provided through a component called GTI (Graphics Technology Interface). This interface interacts with two components of the integrated GPU: Slice Common and the Level 3 cache. Moreover, the graphics will have its own L3 cache of 3 MB, separate from the CPU cache. The connection between GTI and what Intel calls SubSlice — indivisible computing blocks that contain shaders, texture blocks, instruction cache, and other components \u2014 will be established through the Level 3 cache. The design is somewhat reminiscent of streaming multiprocessors in NVIDIA.<\/p>\n

<\/center>
\n\"Details<\/p>\n

Each SubSlice computing block has eight execution units (EUs). Each execution unit has a pair of ALUs, each with four processing pipelines. Overall, the next-generation GT2 graphics will offer 64 EUs. Currently, the existing GT2 type 'integrated graphics' has only 24 EUs, which means an increase of 166%. This will positively affect the performance of Intel's integrated graphics. Additionally, the new Intel architecture includes dedicated hardware for geometry processing, as well as updated external interfaces.<\/p>\n

\"Details<\/p>\n

<\/p>\n

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Source: 3dnews.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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