{"id":30179,"date":"2019-10-31T21:34:00","date_gmt":"2019-10-31T18:34:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski\/"},"modified":"2019-10-31T21:34:00","modified_gmt":"2019-10-31T18:34:00","slug":"asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski","title":{"rendered":"ASICs for machine learning must be designed automatically","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Few would argue that designing custom ASICs is neither a simple nor a quick process. Yet, there is a desire for speed: today you issue an algorithm, and a week later you pick up the finished digital design. The challenge is that highly specialized ASICs are almost a one-off product. They are rarely needed in millions, where you can spend unlimited money and human resources to complete them quickly. Specialized, and therefore most effective ASICs for their tasks, should be cheaper to develop, which is increasingly relevant at this stage of machine learning development. On this front, one cannot rely solely on the baggage accumulated by the computer market and, in particular, the breakthroughs in GPUs for machine learning (ML).<\/p>\n

\"ASICs<\/p>\n

To accelerate the design of ASICs for ML tasks, the DARPA agency is launching a new program \u2013 Real Time Machine Learning (RTML). This real-time machine learning program aims to develop a compiler or software platform that can automatically design the chip architecture for a specific ML framework. The platform should automatically analyze the proposed algorithm for machine learning and the training data set for that algorithm, after which it should generate code in Verilog for creating a specialized ASIC. ML algorithm developers do not possess the knowledge of chip designers, and designers are rarely familiar with the principles of machine learning. The RTML program should facilitate the merging of the strengths of both groups into an automated platform for designing ASICs for machine learning.<\/p>\n

Throughout the lifecycle of the RTML program, the identified solutions will be evaluated in two main areas of application: operation in 5G networks and image processing. Additionally, the RTML program and the created software platforms for the automatic design of ML accelerators will be used for the development and testing of new ML algorithms and datasets. Thus, even before the design of the silicon, the potential of new frameworks can be assessed. The National Science Foundation (NSF) will be the partner of DARPA in the RTML program, which is also addressing issues related to machine learning and the development of ML algorithms. The developed compiler will be transferred to the NSF, and in return, DARPA expects to receive a compiler and a platform for the design of ML algorithms. In the future, hardware design and algorithm creation will be an integrated solution, leading to the emergence of real-time self-learning machine systems.<\/p>\n

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Source: 3dnews.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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