{"id":54142,"date":"2019-12-19T00:00:00","date_gmt":"2019-12-18T21:00:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/blog_prohoster\/utechka-podtverzhdaet-uvelichenie-kesha-vtorogo-urovnya-u-budushhih-protsessorov-intel"},"modified":"2020-02-18T14:02:07","modified_gmt":"2020-02-18T11:02:07","slug":"utechka-podtverzhdaet-uvelichenie-kesha-vtorogo-urovnya-u-budushhih-protsessorov-intel","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/utechka-podtverzhdaet-uvelichenie-kesha-vtorogo-urovnya-u-budushhih-protsessorov-intel","title":{"rendered":"The leak confirms the increase in level 2 cache for future Intel processors","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

In the SiSoftware performance test database, there is a record of testing a server or workstation built on two mysterious six-core Intel processors. These processors are primarily interesting because they have a rather unusual amount of level 2 cache \u2014 1.25 MB per core.<\/p>\n

\"The<\/p>\n

This is five times more compared to the 256 KB L2 cache in Coffee Lake Refresh desktop processors, and two and a half times more than the latest Ice Lake-U chips, which have 512 KB per core. Moreover, this is 25% more than the current Core-X HEDT processors or Xeon Scalable server processors, which have 1 MB of level 2 cache per core.<\/p>\n

\"The<\/p>\n

Therefore, it is only logical to conclude that this processor uses one of Intel's new architectures. It could be the 10nm Ice Lake or Tiger Lake, or the 14nm Rocket Lake. Of the last two architectures, not much is currently known, however, one of the recent leaks<\/a><\/noindex> about Tiger Lake pointed precisely to a level 2 cache of 1.25 MB per core.<\/p>\n

At the same time, another leak<\/a><\/noindex> indicated that the Tiger Lake family would feature only mobile processors with no more than four cores. In contrast, the Rocket Lake chips will offer up to eight cores. Additionally, the six-core chips tested by SiSoftware have less level 3 cache than the previously 'leaked' Tiger Lake.<\/p>\n

<\/center><\/p>\n

Here, one can already assume that the smaller amount of L3 cache could be a result of a less dense placement of transistors, meaning a more 'coarse' manufacturing process. It cannot be ruled out that we are witnessing a transfer of architecture from the more 'fine' 10nm process to the old reliable 14nm. Recently, just about about the release of an unofficial build marked as 'beta.' However, this version is still not available on the official website. It is likely that the company simply allowed the leak.<\/a><\/noindex>, that Rocket Lake will use a new architecture, but on the older process node.<\/p>\n

\"The<\/p>\n

There is another possibility: everything described in the previous two paragraphs may not hold true, and we are actually looking at a system with two 10nm server Ice Lake-SP processors. They could very well have the same cores as the mobile Ice Lake-U, but with a larger amount of level 2 cache per core. This practice is not new for Intel.<\/p>\n

Overall, it's difficult to draw any specific conclusions based on this result. As you can see, there are many possibilities, but little evidence. The one thing we can be sure of is that these six-core processors are not derivatives of Skylake.<\/p>\n

<\/p>\n

<\/center><\/p>\n

\t\t\t\t


\n\t\t\t\t\t\t\t\t<\/center>
Source: 3dnews.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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[…]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-54142","post","type-post","status-publish","format-standard","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Leak confirms the increase of Level 2 cache in future Intel processors | ProHoster","description":"The SiSoftware performance test database contains a record of testing a server or workstation built on two mysterious six-core Intel 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