{"id":73756,"date":"2020-03-11T20:42:30","date_gmt":"2020-03-11T17:42:30","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/lvi-novyj-klass-atak-na-mehanizm-spekulyativnogo-vypolneniya-v-cpu"},"modified":"2020-03-11T20:42:30","modified_gmt":"2020-03-11T17:42:30","slug":"lvi-novyj-klass-atak-na-mehanizm-spekulyativnogo-vypolneniya-v-cpu","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/lvi-novyj-klass-atak-na-mehanizm-spekulyativnogo-vypolneniya-v-cpu","title":{"rendered":"LVI \u2014 a new class of attacks on speculative execution mechanisms in CPUs","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Disclosed<\/a><\/noindex> information about a new class of attacks LVI<\/a><\/noindex> (Load Value Injection, CVE-2020-0551<\/a><\/noindex>) on the speculative execution mechanism in Intel CPUs, which can be used to organize the leakage of keys and secret data from Intel SGX enclaves and other processes.<\/p>\n

The new class of attacks is based on manipulations of the same microarchitectural structures as in the attacks MDS<\/a><\/noindex> (Microarchitectural Data Sampling), Spectre and Meltdown<\/a><\/noindex>However, new attacks are not blocked by existing defenses against Meltdown, Spectre, MDS, and other similar threats. To ensure effective protection against LVI, hardware modifications to the CPU are required. When implementing protection through software by adding the LFENCE instruction after each memory load operation and replacing the RET instruction with POP, LFENCE, and JMP, the overhead becomes prohibitively large \u2014 researchers estimate that complete software protection would lead to a performance drop of 2 to 19 times. <\/p>\n

Partially, the difficulty of blocking the issue is mitigated by the fact that the attack is currently more theoretical than practical (the attack is theoretically possible but very difficult to implement and is only reproducible in synthetic tests).
\nIntel Corporation assigned<\/a><\/noindex> the problem a moderate danger level (5.6 out of 10) and released<\/a><\/noindex> a firmware and SDK update for the SGX environment, in which an attempt was made to block the attack through a workaround. The proposed attack methods are currently applicable only to Intel processors, but the possibility of adapting LVI to other processors susceptible to Meltdown-class attacks cannot be ruled out.<\/p>\n

The problem was identified in April last year by researcher Jo Van Bulck from KU Leuven, after which, with the participation of 9 researchers from other universities, five basic methods of attack were developed, each allowing for more specific variants<\/a><\/noindex>. Independently, in February of this year, researchers from Bitdefender also discovered<\/a><\/noindex> reported one variant of the LVI attack to Intel. The attack variants differ in the use of various microarchitectural structures, such as the Store Buffer (SB), Line Fill Buffer (LFB), FPU context-switch buffer, and Level 1 Data Cache (L1D), previously used in attacks like ZombieLoad<\/a><\/noindex>, RIDL<\/a><\/noindex>, Fallout<\/a><\/noindex>, LazyFP<\/a><\/noindex>, Foreshadow<\/a><\/noindex> and Meltdown<\/a><\/noindex>.<\/p>\n

\"LVI<\/a><\/noindex><\/center><\/p>\n

The main distinction<\/a><\/noindex> LVI from MDS attacks refers to how MDS manipulates the definition of the contents of microarchitectural structures that remain in the cache after speculative exception handling (fault) or load and store operations, while
\nLVI attacks allow the attacker to substitute their data into microarchitectural structures to influence the subsequent speculative execution of the victim's code. Through these manipulations, the attacker can extract the contents of closed data structures in other processes while executing specific code on the target CPU core.<\/p>\n

\"LVI<\/a><\/noindex><\/center><\/p>\n

For exploitation of the issue<\/a><\/noindex> in the victim process's code must occur<\/a><\/noindex> special sequences of code (gadgets) where a value controlled by the attacker is loaded, and loading this value leads to exceptions (fault, abort, or assist), which discard the result and re-execute the instruction. During exception handling, a speculative window occurs, during which data being processed in the gadget leaks. Specifically, the processor begins to speculatively execute a piece of code (gadget), then determines that the prediction was incorrect and rolls back operations to their original state, but the data processed during speculative execution settles in the L1D cache and microarchitectural buffers, making it accessible for extraction using known side-channel residual data detection methods.<\/p>\n

The exception 'assist', unlike 'fault', is handled internally by the processor without calling software handlers. Assist can occur, for instance, when there is a need to update the A (Accessed) or D (Dirty) bits in the memory page table. The main challenge in attacking other processes lies in how to initiate the occurrence of assist by manipulating the victim process. Currently, there are no reliable methods to achieve this, but it cannot be ruled out that such methods may be found in the future. The possibility of carrying out an attack is currently confirmed only for Intel SGX enclaves; other scenarios remain theoretical or reproducible under synthetic conditions (requiring the addition of specific gadgets to the code).<\/p>\n

\"LVI<\/a><\/noindex><\/center><\/p>\n

\"LVI<\/a><\/noindex><\/center><\/p>\n

Possible attack vectors:<\/p>\n