{"id":74591,"date":"2020-03-18T20:42:50","date_gmt":"2020-03-18T17:42:50","guid":{"rendered":"https:\/\/prohoster.info\/blog\/administrirovanie\/pamyat-na-magnitnyh-serdechnikah-v-rakete-saturn-5"},"modified":"2020-03-18T20:42:50","modified_gmt":"2020-03-18T17:42:50","slug":"pamyat-na-magnitnyh-serdechnikah-v-rakete-saturn-5","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/administrirovanie\/pamyat-na-magnitnyh-serdechnikah-v-rakete-saturn-5","title":{"rendered":"Magnetic core memory in the Saturn V rocket","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\"Magnetic
\nThe computer used in the launch vehicle (Launch Vehicle Digital Computer, LVDC) played a key role in the Apollo lunar program, controlling the Saturn V rocket. Like most computers of its time, it stored data in tiny magnetic cores. In this article, Cloud4Y discusses the LVDC memory module from its luxurious collection <\/a><\/noindex>by Steve Jurvetson. <\/i><\/a><\/noindex><\/p>\n

This memory module was upgraded in the mid-1960s. It was created using surface-mount components, hybrid modules, and flexible connections, making it significantly smaller and lighter than typical computer memory of that era. However, the memory module could only store 4,096 words of 26 bits each.<\/p>\n

\"Magnetic
\nMagnetic core memory module. This module stores 4K words of 26 bits of data and 2 bits of parity. With four memory modules providing a total capacity of 16,384 words, it weighs 2.3 kg and measures 14 cm \u00d7 14 cm \u00d7 16 cm.<\/i><\/p>\n

The lunar flight began on May 25, 1961, when President Kennedy announced that America would land a man on the Moon by the end of the decade. A three-stage rocket, the Saturn V, which is the most powerful rocket ever built, was used for this. The Saturn V was managed and controlled by the computer ( here are more details<\/a><\/noindex> ) of the launch vehicle's third stage, starting from launch into Earth orbit and then proceeding towards the Moon. (At this point, the Apollo spacecraft separated from the Saturn V rocket, completing the task of the LVDC).<\/p>\n

\"Magnetic
\nThe LVDC is mounted in a support frame. Round connectors can be seen on the front of the computer. Eight electrical connectors and two liquid cooling connectors were used.<\/i><\/p>\n

The LVDC was just one of several computers onboard Apollo. It was connected to the flight control system, a 45-kilogram analog computer. The Apollo Guidance Computer (AGC) navigated the spacecraft to the lunar surface. The command module contained one AGC, while the lunar module housed a second AGC along with the Abort navigation system and a backup emergency computer.<\/p>\n

\"Magnetic
\nSeveral computers were onboard Apollo<\/i> <\/p>\n

Unit Logic Devices (ULD)<\/h2>\n

\nLVDC was created using an interesting hybrid technology called ULD, unit load device. Although they resembled integrated circuits externally, ULD modules contained several components. They used simple silicon crystals, each containing just one transistor or two diodes. These matrices, along with printed thick-film resistors, were mounted on a ceramic plate to implement circuits like a logic gate. These modules were a variant of SLT modules (Solid Logic Technology<\/a><\/noindex>), developed for IBM's popular S\/360 computer series. IBM began developing SLT modules in 1961, before integrated circuits became commercially viable, and by 1966, IBM was producing over 100 million SLT modules annually.<\/p>\n

ULD modules were significantly smaller than SLT modules, as seen in the photograph below, making them more suitable for a compact space computer. ULD modules used ceramic cover plates instead of metallic pins in SLT and had metal contacts on the top surface instead of pins. Clips on the board held the ULD module in place and connected to these contacts. <\/p>\n

Why did IBM use SLT modules instead of integrated circuits? The main reason was that integrated circuits were still in their infancy, having been invented in 1959. By 1963, SLT modules had advantages in cost and performance over integrated circuits. However, SLT modules were often seen as outdated compared to integrated circuits. One advantage of SLT modules over integrated circuits was that the resistors in SLT were much more accurate than those in integrated circuits. During manufacturing, thick-film resistors in SLT modules underwent meticulous sandblasting to remove the resistive film until the desired resistance was achieved. SLT modules were also cheaper than comparable integrated circuits in the 1960s.<\/p>\n

LVDC and related equipment used over 50 different types of ULD.<\/p>\n

\"Magnetic
\nSLT modules (left) are significantly larger than ULD modules (right). The size of ULD is 7.6 mm \u00d7 8 mm.<\/i> <\/p>\n

The photo below shows the internal components of the ULD module. On the left, you can see conductors on the ceramic plate connected to four tiny square silicon crystals. It resembles a printed circuit board, but keep in mind that it is much smaller than a fingernail. The black rectangles on the right are thick-film resistors printed on the underside of the plate.<\/p>\n

\"Magnetic
\nULD, top and bottom view. The silicon crystals and resistors are visible. While the SLT modules had resistors on the top surface, the ULD modules had resistors on the bottom, which increased density as well as cost.<\/i> <\/p>\n

The photograph below shows a silicon crystal from the ULD module that implemented two diodes. The sizes are exceptionally small, with sugar crystals next to it for comparison. The crystal had three external connections through soldered copper balls to three circles. The two lower circles (the anodes of the two diodes) were doped (the darker areas), while the upper right circle was the cathode, connected to the base.<\/p>\n

\"Magnetic
\nA photograph of a two-diode silicon crystal next to sugar crystals.<\/i> <\/p>\n

How Magnetic Core Memory Works<\/h2>\n

\nMagnetic core memory was the primary form of data storage in computers from the 1950s until it was replaced by semiconductor memory in the 1970s. The memory was made up of tiny ferrite rings called cores. The ferrite rings were arranged in a rectangular matrix with two to four wires passing through each ring for reading and writing information. The rings allowed for the storage of one bit of information. A core would be magnetized by a pulse of current through the wires that passed through the ferrite ring. The direction of magnetization of one core could be changed by sending a pulse in the opposite direction.<\/p>\n

To read the core value, the current pulse switched the ring to state 0. If the core had previously been in state 1, the changing magnetic field would create a voltage in one of the wires passing through the cores. However, if the core was already in state 0, the magnetic field would not change, and the voltage on the reading wire would not increase. Thus, the bit value in the core was read by resetting it to zero and checking the voltage on the reading wire. An important feature of memory on magnetic cores was that the reading process destroyed its value, so the core needed to be 'rewritten.'<\/p>\n

Using a separate wire to change the magnetization of each core was inconvenient, but in the 1950s, ferrite memory was developed based on the principle of current coincidence. The four-wire scheme - X, Y, read, inhibit - became standard. The technology utilized a special property of the cores called hysteresis: a small current does not affect ferrite memory, but a current above a threshold value would magnetize the core. By supplying power with half the required current to one X line and one Y line, only the core where both lines intersect received enough current to remagnetize, while other cores remained untouched. <\/p>\n

\"Magnetic
\nThis is what the IBM 360 Model 50 memory looked like. The LVDC and Model 50 used cores of one type, known as 19-32, because their internal diameter was 19 mil (0.4826 mm), and their external diameter was 32 mil (0.8 mm). In this photograph, it can be seen that three wires pass through each core, but the LVDC used four wires.<\/i> <\/p>\n

The photo below shows a rectangular memory matrix of the LVDC. This matrix has 128 X wires running vertically and 64 Y wires running horizontally, with a core at each intersection. The single reading wire crosses all the strands in parallel with the Y wires. The writing wire and the inhibit wire run through all the strands in parallel with the X wires. The wires intersect in the middle of the matrix, which reduces induced noise because the noise from one half neutralizes the noise from the other half.<\/p>\n

\"Magnetic
\nA single LVDC ferrite memory matrix containing 8192 bits. Connection to other matrices is made through pins on the outer side.<\/i> <\/p>\n

The matrix above had 8192 elements, each storing one bit. To retain a memory word, several basic matrices were stacked together, one for each bit in the word. The X and Y wires zigzagged across all the basic matrices. Each matrix had a separate reading line and a dedicated write inhibit line. The LVDC memory used a stack of 14 basic matrices, storing a 13-bit 'syllable' along with a parity bit. <\/p>\n

\"Magnetic
\nThe LVDC stack consists of 14 basic matrices.<\/i> <\/p>\n

Writing to memory on magnetic cores required additional wires known as inhibit lines. Each matrix had one inhibit line that penetrated all the cores within it. During the writing process, current flowed through the X and Y lines, remagnetizing the selected rings (one per plane) to state 1, retaining all 1s in the word. To write a 0 at a bit position, the line was powered with half the current, opposite to the X line. As a result, the cores remained at value 0. Thus, the inhibit line prevented the core from flipping to 1. Any desired word could be written to memory by activating the corresponding inhibit lines.<\/p>\n

LVDC Memory Module<\/h2>\n

\nHow is the LVDC memory module physically constructed? At the center of the memory module is a stack of 14 previously shown ferromagnetic memory matrices. It is surrounded by several boards with circuitry for controlling the X and Y wires, inhibit lines, bit reading lines, error detection, and generating the necessary clock signals. <\/p>\n

Generally, most of the circuitry related to memory is in the computer's LVDC logic rather than in the memory module itself. In particular, the computer logic contains registers for storing addresses and data words, and for converting between serial and parallel. It also contains circuitry for reading from bit reading lines, error checking, and clocking.<\/p>\n

\"Magnetic
\nMemory module indicating key components. MIB (Multilayer Interconnection Board) is a 12-layer printed circuit board.<\/i> <\/p>\n

Memory driver board Y<\/h2>\n

\nA word in memory on magnetic cores is selected by passing the corresponding X and Y lines through the main stack of boards. Let's start by describing the Y-driver scheme and how it generates a signal through one of the 64 Y-lines. Instead of 64 separate driver circuits, the module reduces the number of circuits by using 8 'high' drivers and 8 'low' drivers. They are connected in a 'matrix' configuration, so each combination of high and low drivers selects different rows. Thus, 8 'high' and 8 'low' drivers select one of the 64 (8 \u00d7 8) Y-lines. <\/p>\n

\"Magnetic
\nThe Y driver board (front view) controls the Y selection lines in the stack of boards.<\/i> <\/p>\n

In the photo below, you can see some of the ULD modules (white) and pairs of transistors (golden) that control the Y selection lines. The 'EI' module is the heart of the driver: it applies a direct voltage pulse (E) or allows a direct current pulse (I) to pass through the selection line. The selection line is managed by activating the EI module in voltage mode at one end of the line and the EI module in current mode at the other end. The result is a pulse with the correct voltage and current sufficient to remagnetize the core. A large pulse is required to flip it; the voltage pulse is fixed at 17 volts, while the current ranges from 180 mA to 260 mA depending on the temperature. <\/p>\n

\"Magnetic
\nA macro photo of the Y driver board showing six ULD modules and six pairs of transistors. Each ULD module is labeled with the IBM part number, module type (e.g., 'EI'), and a code, the significance of which is unclear.<\/i> <\/p>\n

The board is also equipped with error tracking modules (ED) that detect when more than one Y selection line is activated simultaneously. The ED module uses a simple half-analog solution: it sums the input voltages using a network of resistors. If the resulting voltage exceeds the threshold, the switch activates. <\/p>\n

Under the driver board is a diode matrix containing 256 diodes and 64 resistors. This matrix converts 8 upper and 8 lower pairs of signals from the driver board into connections with 64 Y-lines that pass through the main stack of boards. Flexible cables at the top and bottom of the board connect the board to the diode matrix. Two flexible cables on the left (not visible in the photo) and two buses on the right (one is visible) connect the diode matrix to the core array. The flexible cable visible on the left connects the Y-board to the rest of the computer via the input\/output board, while a small flexible cable in the lower right corner connects to the clock generator board.<\/p>\n

Memory Driver Board X<\/h2>\n

\nThe circuit for controlling the X lines is similar to that of the Y lines, except that there are 128 X lines and 64 Y lines. Since there are twice as many X wires, the module has a second X driver board located underneath it. Although the X and Y boards have the same components, the routing is different.<\/p>\n

\"Magnetic
\nThis board and the similar one below it control the selected X rows in the stack of core boards.<\/i> <\/p>\n

The photo below shows that some components on the board were damaged. One of the transistors is misaligned, the ULD module is broken in half, and another is shattered. The routing is visible at the broken module, and one of the tiny silicon chips can be seen (on the right). This photo also shows traces of vertical and horizontal conductive paths on the 12-layer printed circuit board.<\/p>\n

\"Magnetic
\nClose-up of the damaged area of the board<\/i> <\/p>\n

Under the X driver boards is the X diode matrix, which contains 288 diodes and 128 resistors. The X diode matrix uses a topology different from that of the Y diode board to avoid doubling the number of components. Like the Y diode board, this board has components installed vertically between two printed circuit boards. This method is known as 'cordwood' and allows for compact component packaging.<\/p>\n

\"Magnetic
\nMacro photo of the X diode matrix shows vertically installed diodes using the cordwood method between two printed circuit boards. Two X driver boards are positioned above the diode board, separated from it by polyurethane foam. Note that the printed circuit boards are placed very close to each other.<\/i> <\/p>\n

Memory Amplifiers<\/h2>\n

\nThe photo below shows the read amplifier board. It has 7 channels for reading 7 bits from the memory stack; the identical board below processes another 7 bits, totaling 14 bits. The purpose of the read amplifier is to detect a weak signal (20 millivolts) generated by the magnetizable core and turn it into a 1-bit output. Each channel consists of a differential amplifier and a buffer, followed by a differential transformer and an output latch. On the left, a 28-wire flexible cable connects to the memory stack, routing two ends of each reading wire to the amplifier circuit, starting with the MSA-1 module (memory read amplifier). The individual components are resistors (brown cylinders), capacitors (red), transformers (black), and transistors (gold). Data bits exit the read amplifier boards through the flexible cable on the right.<\/p>\n

\"Magnetic
\nThe read amplifier board at the top of the memory module. This board amplifies signals from the sensing wires to create output bits.<\/i> <\/p>\n

Write inhibit line driver.<\/h2>\n

\nInhibit drivers are used for writing to memory and are located on the underside of the main module. There are 14 inhibit lines, one for each matrix in the stack. To write a 0 bit, the corresponding inhibit driver is activated, and current through the inhibit line prevents the core from switching to 1. Each line is driven by modules ID-1 and ID-2 (write inhibit line driver) and a pair of transistors. High-precision 20.8 Ohm resistors at the top and bottom of the board regulate the inhibit current. A 14-wire flexible cable on the right connects the drivers to the 14 inhibit wires in the stack of cores.<\/p>\n

\"Magnetic
\nThe inhibit board at the bottom of the memory module. This board generates 14 inhibit signals used during writing.<\/i> <\/p>\n

Clock driver memory.<\/h2>\n

\nThe clock driver consists of a pair of boards that generate synchronization signals for the memory module. Once the computer starts an operation with memory, various synchronizing signals used by the memory module are asynchronously generated by the module's clock driver. The clock driver boards are located at the bottom of the module, between the stack and the inhibit board, making them less visible.<\/p>\n

\"Magnetic
\nClock driver boards are located below the main memory stack but above the blocking board.<\/i> <\/p>\n

The blue components on the board in the photo above are multi-turn potentiometers, presumably for adjusting time or voltage. Resistors and capacitors are also visible on the boards. The schematic shows several MCD (Memory Clock Driver) modules, but no modules are visible on the boards. It's hard to say if this is due to limited visibility, changes in the schematic, or the presence of another board with these modules.<\/p>\n

Memory I\/O panel<\/h2>\n

\nThe last board of the memory module is the I\/O panel, which distributes signals between the memory module boards and the rest of the LVDC computer. The green 98-pin connector at the bottom connects to the LVDC memory chassis, providing signals and power from the computer. Most of the plastic connectors are broken, exposing the contacts. The distribution board is connected to this connector by two 49-pin flexible cables at the bottom (only the front cable is visible). Other flexible cables distribute signals to the X-driver board (left), Y-driver board (right), read amplifier board (top), and disable board (bottom). 20 capacitors on the board filter the power supplied to the memory module.<\/p>\n

\"Magnetic
\nI\/O board between the memory module and the rest of the computer. The green connector at the bottom connects to the computer, and these signals are routed through flat cables to other parts of the memory module.<\/i> <\/p>\n

Output<\/h2>\n

\nThe main LVDC memory module provided compact, reliable storage. Up to 8 memory modules could be housed in the lower half of the computer. This allowed the computer to store 32 kilowords. <\/a><\/noindex>26-bit words or 16 kilowords in redundant fault-tolerant 'duplex' mode.<\/p>\n

One interesting feature of the LVDC was that memory modules could be mirrored for reliability. In 'duplex' mode, each word was stored in two memory modules. If one module encountered an error, the correct word could be retrieved from the other module. While this ensured reliability, it halved the memory capacity. Alternatively, memory modules could be used in 'simplex' mode, where each word is stored once.<\/p>\n

\"Magnetic
\nLVDC accommodated up to eight CPU memory modules<\/i> <\/p>\n

The magnetic core memory module illustrates the time when a 5-pound (2.3 kg) module was needed to store 8 KB. However, this memory was quite advanced for its time. Such devices fell out of use in the 1970s with the advent of semiconductor DRAM.<\/p>\n

The contents of RAM are retained when power is lost, so it is quite possible that the module still holds software from the last time the computer was used. Yes, something interesting could still be found there even after decades. It would be intriguing to try to recover this data, but a damaged circuit presents a problem, so the content is likely to remain inaccessible for decades.<\/p>\n

What else is useful to read in the blog Cloud4Y<\/a><\/noindex><\/b><\/p>\n

\u2192 Easter eggs on Swiss topographic maps<\/a><\/noindex>
\n\u2192 Computer Brands of the '90s, Part 1<\/a><\/noindex>
\n\u2192 How a Hacker's Mom Smuggled into Prison and Infected the Boss's Computer <\/a><\/noindex>
\n\u2192 Network connection diagnostics on the virtual EDGE router.<\/a><\/noindex>
\n\u2192 How the bank 'broke.'<\/a><\/noindex><\/p>\n

Subscribe to our Telegram<\/a><\/noindex>-channel to not miss the next article! We write no more than twice a week and only about essential matters. We also remind you that Cloud4Y can provide secure and reliable remote access to business applications and information necessary to ensure business continuity. Remote work is an additional barrier to the spread of coronavirus. Details are available from our managers.
\n
Source: habr.com<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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