{"id":77492,"date":"2020-04-10T19:42:45","date_gmt":"2020-04-10T17:42:45","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe"},"modified":"2020-04-10T19:42:45","modified_gmt":"2020-04-10T17:42:45","slug":"poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe","title":{"rendered":"Beware, ARM? New 64-bit cores from Synopsys ARC will triple performance","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Few people know that the ARC processor architecture is one of the most widely used architectures alongside ARM, MIPS, and x86. Developed in the 1980s, the ARC architecture is applied in various microcontrollers for a broad range of high-tech products, with around 1.5 billion<\/a><\/noindex> devices produced each year.<\/p>\n

Recently, Synopsys announced a new generation of 32-bit and 64-bit ARC processor cores, promising to triple performance compared to their predecessors and enabling the construction of systems-on-chip with 12 cores. Thus, these new cores will allow Synopsys to compete with ARM in several new areas.<\/p>\n

«Embedded applications such as controllers for solid-state drives or networking equipment are becoming increasingly complex, requiring significant performance increases while maintaining limited power consumption and size,» said John Koeter, senior vice president of marketing and strategy in the field of intellectual property at Synopsys. «With the release of the new ARCv3 architecture and ARC HS5x and HS6x cores, developers will be able to meet the growing performance demands of their SoCs today and in the future.»<\/p>\n

\"Beware,
\n<\/center><\/p>\n

The new Synopsys DesignWare ARC processor families include 32-bit cores HS56\/HS57D\/HS58<\/a><\/noindex> and 64-bit cores HS66\/HS68<\/a><\/noindex>. The newly announced processors are intended for a wide range of applications, such as controllers for solid-state drives (SSDs), network controllers, vehicle autopilots, infotainment systems for cars, and many more. Considering the increasing memory requirements, the 64-bit ARC HD6x will allow for systems with 4.5 PB of DRAM, while ARC HD5x-based devices will have to settle for smaller capacities. However, the actual amounts of supported memory are likely to be dictated by the operating system in use, while the visible benefits of 64-bit CPUs will include a wider pipeline and a larger register file.<\/p>\n

Regarding the DesignWare ARC HS5x and DesignWare ARC HS6x architectures, they support the ARCv3 instruction set, which can be extended with APEX (ARC Processor EXtensions) instructions if any client needs something specific. Additionally, the ARC HS57D is equipped with the ARCv3DSP digital signal processor supporting 150 instructions. The new cores have a 10-stage pipeline, can execute two instructions per clock cycle, and are equipped with a 128-bit floating-point operation module. Moreover, the most advanced versions of the cores support a level 2 (L2) cache of up to 16 MB.<\/p>\n

\"Beware,<\/p>\n

When it comes to performance, Synopsys claims 3 DMIPS per MHz for integer computations, as well as 5.1 CoreMark per MHz, which is quite impressive for compact cores with minimal power consumption. Thus, 3 DMIPS per MHz — is higher than that of relatively powerful processors. Cortex-A55<\/a><\/noindex>, while 5.1 CoreMark per MHz — is higher than any other. ARM microcontroller.<\/a><\/noindex><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

The Synopsys DesignWare ARC HS5x and HS6x processor cores
<\/strong><\/p>\n<\/td>\n<\/tr>\n

<\/td>\nHS5x<\/td>\nHS6x<\/td>\n<\/tr>\n
<\/td>\nHS56<\/td>\nHS57D<\/td>\nHS58<\/td>\nHS66<\/td>\nHS68<\/td>\n<\/tr>\n
Instruction set<\/td>\nARCv3<\/td>\n<\/tr>\n
APEX instructions<\/td>\nSupported<\/td>\n<\/tr>\n
Bit width<\/td>\n32-bit<\/td>\n64-bit<\/td>\n<\/tr>\n
Instructions per cycle<\/td>\n2<\/td>\n<\/tr>\n
Pipeline length<\/td>\n10 stages<\/td>\n<\/tr>\n
DSP<\/td>\n\u2014<\/td>\nARCv3DSP
150 instructions<\/td>\n		\u2014<\/td>\n\u2014<\/td>\n\u2014<\/td>\n<\/tr>\n
FPU accuracy<\/td>\nFP16, FP32, FP64<\/td>\n<\/tr>\n
Processor cluster<\/td>\n12 cores<\/td>\n<\/tr>\n
Accelerators per cluster<\/td>\n16 accelerators<\/td>\n<\/tr>\n
L1<\/td>\nInstruction cache + Data cache<\/td>\n<\/tr>\n
L2<\/td>\n\u2014<\/td>\n\u2014<\/td>\n16 MB<\/td>\n\u2014<\/td>\n16 MB<\/td>\n<\/tr>\n
Maximum memory size<\/td>\n64 GB (depends on OS)<\/td>\n4.5 Petabytes<\/td>\n<\/tr>\n
Frequency (on 16FFC process)<\/td>\n1.8 GHz<\/td>\n<\/tr>\n
DMIPS<\/td>\n5400 DMIPS per core \/ 3 DMIPS per MHz<\/td>\n<\/tr>\n
CoreMark<\/td>\n9180 CoreMark per core \/ 5.1 CoreMark per MHz<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

One of the key features of the new DesignWare ARC HS5x and DesignWare ARC HS6x family is the ability to create system-on-chip (SoC) designs with 12 general-purpose processor cores and 16 specialized accelerators. Each core\/accelerator in such a processor operates at its own clock frequency and uses its own power subsystem to maximize energy efficiency. Along with the new cores, Synopsys also offers an on-chip cache-coherent interconnect with a data transfer rate of 800 GB\/s. <\/p>\n

Such SoCs based on the ARC architecture are not very common today, but considering the promising processors for autopilot systems, data storage, data flow management, multicore processing, and various accelerators will be very timely. The latter would allow Synopsys to compete with ARM cores for a place in SoCs for the mentioned applications, which has not happened until now. For instance, Starblaze, a manufacturer of solid-state drives, has already shown interest in the DesignWare ARC HS5x and DesignWare ARC HS6x cores. <\/p>\n

«Developers of high-performance embedded solutions are constantly facing new challenges in achieving high performance while utilizing large memory volumes and adhering to power consumption and size constraints,» said Bruce Cheng, chief scientist at Starblaze. «The capabilities of the new 32-bit ARC HS5x and 64-bit HS6x processors from Synopsys in terms of multicore support will enable us to achieve a new level of energy efficiency not offered by other processors currently available on the market.»<\/p>\n

\"Beware,<\/p>\n

Synopsys will begin offering the ARC HS56, HS57D, HS58, HS66, HS68 cores, as well as their multiprocessor versions HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP, starting in the third quarter of 2020. In addition, the company will offer the ARC MetaWare Development Toolkit for chip development based on these cores, along with a simulator and verifier to validate the SoC functionality before physical implementation. As for operating system support, the new cores will be compatible with a number of Linux distributions, Zephyr, as well as various proprietary operating systems.<\/p>\n

<\/p>\n

<\/center><\/p>\n

\t\t\t\t


\n\t\t\t\t\t\t\t\t<\/center>
Source: 3dnews.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041d\u0435\u043c\u043d\u043e\u0433\u0438\u0435 \u0437\u043d\u0430\u044e\u0442, \u0447\u0442\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043d\u0430\u044f \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 ARC \u044f\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u043e\u0434\u043d\u043e\u0439 \u0438\u0437 \u0441\u0430\u043c\u044b\u0445 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u0435\u043d\u043d\u044b\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440 \u043d\u0430\u0440\u044f\u0434\u0443 \u0441 ARM, MIPS \u0438 x86. \u0420\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d\u043d\u0430\u044f \u0432 1980-\u0445 \u0433\u043e\u0434\u0430\u0445, \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 ARC \u043f\u0440\u0438\u043c\u0435\u043d\u044f\u0435\u0442\u0441\u044f \u0432 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0445 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430\u0445 \u0434\u043b\u044f \u0448\u0438\u0440\u043e\u0447\u0430\u0439\u0448\u0435\u0433\u043e \u0441\u043f\u0435\u043a\u0442\u0440\u0430 \u0432\u044b\u0441\u043e\u043a\u043e\u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0447\u043d\u043e\u0439 \u043f\u0440\u043e\u0434\u0443\u043a\u0446\u0438\u0438, \u0430 \u043a\u0430\u0436\u0434\u044b\u0439 \u0433\u043e\u0434 \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 ARC \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0441\u044f \u043e\u043a\u043e\u043b\u043e 1,5 \u043c\u0438\u043b\u043b\u0438\u0430\u0440\u0434\u0430 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432. \u041d\u0430 \u0434\u043d\u044f\u0445 \u043a\u043e\u0440\u043f\u043e\u0440\u0430\u0446\u0438\u044f Synopsys \u0430\u043d\u043e\u043d\u0441\u0438\u0440\u043e\u0432\u0430\u043b\u0430 \u043d\u043e\u0432\u043e\u0435 \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u0435 32- \u0438 64-\u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043d\u044b\u0445 […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":77493,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-77492","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Watch out, ARM? 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