{"id":84726,"date":"2020-06-10T13:42:19","date_gmt":"2020-06-10T11:42:19","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v"},"modified":"2020-06-10T13:42:19","modified_gmt":"2020-06-10T11:42:19","slug":"mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","title":{"rendered":"The microkernel seL4 is mathematically verified for the RISC-V architecture.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Organization RISC-V Foundation has announced<\/a><\/noindex> on the verification of the microkernel operation seL4<\/a><\/noindex> on systems with the RISC-V instruction set architecture. Verification entails mathematical proof<\/a><\/noindex> of the reliability of seL4, which indicates complete compliance with the specifications defined in formal language. The proof of reliability allows the use of<\/a><\/noindex> seL4 in critical systems based on RISC-V RV64 processors that require a high level of reliability and guarantee the absence of failures. Software developers working on top of the seL4 kernel can be fully assured that in the event of a failure in one part of the system, this failure will not propagate to the rest of the system, particularly its critical components. <\/p>\n

Initially, the seL4 microkernel was verified for 32-bit ARM processors and later for 64-bit x86 processors. It is noted that the combination of the open hardware architecture RISC-V with the open microkernel seL4 will achieve a new level of security, as the hardware components could also potentially be fully verified in the future, which is not achievable with proprietary hardware architectures. <\/p>\n

During the verification of seL4, it is assumed that the hardware operates as stated and the specification fully describes the system's behavior. However, in practice, the hardware is not free from bugs, which is well illustrated by the regularly emerging issues in the speculative execution mechanism. Open hardware platforms facilitate the integration of security-related changes \u2014 for example, to block all possible leakage channels through third-party paths, where it is far more effective to eliminate the problem at the hardware level than to seek software workarounds.<\/p>\n

Recall that the architecture seL4 is notable for<\/a><\/noindex> by offloading parts for core resource management into user space and applying the same access control tools for these resources as for user resources. The microkernel does not provide ready-made high-level abstractions for managing files, processes, network connections, etc.; instead, it only provides minimal mechanisms for managing access to physical address space, interrupts, and CPU resources. High-level abstractions and drivers for hardware interaction are implemented separately on top of the microkernel in the form of tasks executed at the user level. Access for these tasks to resources available to the microkernel is organized through rule definition.<\/p>\n

RISC-V offers an open and flexible instruction set architecture that enables the creation of microprocessors for arbitrary applications without requiring royalty fees or imposing usage conditions. RISC-V allows for the development of completely open SoCs and processors. Currently, various companies and communities are producing several dozen variants of microprocessor cores, SoCs, and chips based on the RISC-V specification under different open licenses (BSD, MIT, Apache 2.0). is being developed<\/a><\/noindex> Support for RISC-V has been available since the releases of Glibc 2.27, binutils 2.30, gcc 7, and Linux kernel 4.15.<\/p>\n

<\/a><\/noindex><\/p>\n

Source: opennet.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041e\u0440\u0433\u0430\u043d\u0438\u0437\u0430\u0446\u0438\u044f RISC-V Foundation \u0441\u043e\u043e\u0431\u0449\u0438\u043b\u0430 \u043e \u0432\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u0438 \u0440\u0430\u0431\u043e\u0442\u044b \u043c\u0438\u043a\u0440\u043e\u044f\u0434\u0440\u0430 seL4 \u043d\u0430 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u0445 \u0441 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043e\u0439 \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V. \u0412\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f \u0441\u0432\u043e\u0434\u0438\u0442\u0441\u044f \u043a \u043c\u0430\u0442\u0435\u043c\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u043e\u043c\u0443 \u0434\u043e\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u0443 \u043d\u0430\u0434\u0451\u0436\u043d\u043e\u0441\u0442\u0438 \u0440\u0430\u0431\u043e\u0442\u044b seL4, \u043a\u043e\u0442\u043e\u0440\u043e\u0435 \u0441\u0432\u0438\u0434\u0435\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u0443\u0435\u0442 \u043e \u043f\u043e\u043b\u043d\u043e\u043c \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0438\u0438 \u0437\u0430\u0434\u0430\u043d\u043d\u044b\u043c \u043d\u0430 \u0444\u043e\u0440\u043c\u0430\u043b\u044c\u043d\u043e\u043c \u044f\u0437\u044b\u043a\u0435 \u0441\u043f\u0435\u0446\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f\u043c. \u0414\u043e\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u043e \u043d\u0430\u0434\u0451\u0436\u043d\u043e\u0441\u0442\u0438 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c seL4 \u0432 \u043a\u0440\u0438\u0442\u0438\u0447\u0435\u0441\u043a\u0438 \u0432\u0430\u0436\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u0445 \u043d\u0430 \u0431\u0430\u0437\u0435 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 RISC-V RV64, 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