the previous article<\/a><\/noindex>). This allows for the relatively rapid and inexpensive creation of the simulator itself. The ISA level is also advantageous because it remains more or less stable, unlike, for example, the API\/ABI level, which changes more frequently. Moreover, implementing at the instruction level allows running so-called unmodified binary software, meaning that already compiled code can be executed without any changes, exactly as it is used on real hardware. In other words, you can make a 'dump' of a hard drive, specify it as an image for the model in the full-platform simulator, and \u2013 voila! \u2013 the OS and other programs are loaded into the simulator without any additional actions. <\/p>\nSimulator Performance <\/h3>\n
Here it is appropriate to touch on the topic of simulator performance. It is usually measured in IPS (instructions per second), more precisely in MIPS (millions of IPS), that is, the number of CPU instructions executed by the simulator in one second. At the same time, the speed of simulation also depends on the performance of the system on which the simulation itself operates. Therefore, it may be more accurate to speak of the 'slowdown' of the simulator compared to the original system. <\/p>\n
The most common full-platform simulators on the market, such as QEMU, VirtualBox, or VMware Workstation, offer decent performance. Users may not even notice that they are operating within a simulator. This is possible due to a special virtualization capability implemented in modern processors, binary translation algorithms, and other interesting features. This is all a topic for a separate article, but to keep it brief, virtualization is a hardware feature of contemporary processors that allows simulators to execute instructions directly on the real processor, provided that the simulator and processor architectures are similar. Binary translation is the conversion of guest machine code into host code followed by execution on the actual processor. As a result, simulation is only marginally slower\u2014by a factor of 5 to 10, or often runs at the same speed as the real system. However, many factors influence this speed. For example, if we want to simulate a system with several dozen processors, the speed will drop significantly, potentially by that many times. On the other hand, simulators like Simics in their latest versions support multi-processor host hardware and effectively parallelize the simulated cores onto the real processor cores. <\/p>\n
When it comes to the speed of microarchitectural simulation, it is usually several orders of magnitude slower, about 1000 to 10,000 times slower than execution on a regular computer without simulation. Implementations at the logic level are even slower by several orders. Therefore, FPGAs are used as emulators at this level, which significantly enhances performance. <\/p>\n
The chart below illustrates the approximate relationship between simulation speed and model detail. <\/p>\n
Cycle-accurate simulation <\/h3>\n \nDespite their relatively low execution speed, microarchitectural simulators are quite common. Modeling the internal blocks of a processor is necessary to accurately simulate the execution time of each instruction. Here, a misunderstanding may arise\u2014after all, why not just program the execution time for each instruction? However, such a simulator would operate very inaccurately, as the execution time for the same instruction can vary from call to call. <\/p>\n
A simple example is the memory access instruction. If the requested memory cell is available in the cache, the execution time will be minimal. If the information is not in the cache (a 'cache miss'), this significantly increases the execution time of the instruction. Thus, a cache model is essential for accurate simulation. However, the cache model is not the only consideration. The processor will not simply wait for data to be retrieved from memory when it is absent from the cache. Instead, it will start executing the next instructions, choosing those that do not depend on the read result from memory. This is the so-called out-of-order execution (OOO), necessary to minimize the processor's idle time. Modeling the corresponding blocks of the processor will help take all of this into account when calculating instruction execution times. Among these instructions that are executed while waiting for the memory read result, there may be a conditional branch operation. If the result of the condition is unknown at that moment, then again, the processor does not halt execution; rather, it makes a 'guess', carries out the corresponding branch, and continues to proactively execute instructions from the branch point. Such a unit, known as a branch predictor, must also be implemented in the microarchitectural simulator. <\/p>\n
The image below shows the main blocks of the processor. It is not necessary to know this; it is provided merely to illustrate the complexity of the microarchitectural implementation. <\/p>\n
As mentioned above, cycle-accurate simulation is very slow, which is why it is only used to investigate specific aspects of program operation where it is necessary to determine the actual execution speed of programs and assess the future performance of the device being modeled. <\/p>\n
Meanwhile, a functional simulator is used for simulating the remainder of the program's execution time. How does this combined usage occur in reality? First, a functional simulator is launched, where the OS and everything needed to run the examined program is loaded. We are not interested in the OS itself, nor in the initial stages of launching the program, its configuration, and so on. However, we cannot skip these parts and immediately jump to executing the program from the middle. Therefore, all these preliminary stages are run on the functional simulator. Once the program has executed to the point of interest, there are two options. The model can be switched to cycle accurate and execution can continue. The simulation mode that uses executable code (i.e., regular compiled program files) is called execution driven simulation. This is the most common type of simulation. Another approach is also possible \u2013 simulation based on traces (trace driven simulation). <\/p>\n
Trace driven simulation <\/h3>\n \nIt consists of two steps. Using a functional simulator or on a real system, a log of the program's actions is collected and recorded into a file. This log is called a trace. Depending on what is being investigated, the trace may include executable instructions, memory addresses, port numbers, and interrupt information. <\/p>\n
The next step is the 'tracing' where the cycle-accurate simulator reads the trace and executes all instructions recorded in it. In the end, we obtain the execution time of this piece of software, as well as various characteristics of this process, such as the cache hit rate. <\/p>\n
An important feature of working with traces is determinism, meaning that by running the simulation in the manner described above, we reproduce the same sequence of actions time and again. This allows us to explore how various parameters of the model (cache sizes, buffers, and queues) and using different internal algorithms or tuning them affect system performance, and which option yields the best results. All this can be done with a prototype model of the device before creating a real hardware prototype. <\/p>\n
The complexity of this approach lies in the need for a preliminary run of the application and trace collection, as well as the enormous size of the trace file. The advantages include the fact that it is enough to model only the part of the device or platform that is of interest, whereas execution simulation typically requires a full model. <\/p>\n
Thus, in this article, we explored the features of full-platform simulation, discussed the speed of implementations at different levels, cycle-accurate simulation, and traces. In the next article, I will describe the main scenarios for using simulators, both for personal use and from the perspective of development in large companies.habr.com<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"\u0412\u043e \u0432\u0442\u043e\u0440\u043e\u0439 \u0447\u0430\u0441\u0442\u0438 \u0441\u0442\u0430\u0442\u044c\u0438 \u043e \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430\u0445 \u043a\u043e\u043c\u043f\u044c\u044e\u0442\u0435\u0440\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c \u043f\u0440\u043e\u0434\u043e\u043b\u0436\u0443 \u0440\u0430\u0441\u0441\u043a\u0430\u0437\u044b\u0432\u0430\u0442\u044c \u0432 \u043f\u0440\u043e\u0441\u0442\u043e\u0439 \u043e\u0437\u043d\u0430\u043a\u043e\u043c\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0439 \u0444\u043e\u0440\u043c\u0435 \u043e \u043a\u043e\u043c\u043f\u044c\u044e\u0442\u0435\u0440\u043d\u044b\u0445 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430\u0445, \u0430 \u0438\u043c\u0435\u043d\u043d\u043e \u043e \u043f\u043e\u043b\u043d\u043e\u043f\u043b\u0430\u0442\u0444\u043e\u0440\u043c\u0435\u043d\u043d\u043e\u0439 \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438, \u0441 \u043a\u043e\u0442\u043e\u0440\u043e\u0439 \u0447\u0430\u0449\u0435 \u0432\u0441\u0435\u0433\u043e \u0441\u0442\u0430\u043b\u043a\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u043e\u0431\u044b\u0447\u043d\u044b\u0439 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c, \u0430 \u0442\u0430\u043a\u0436\u0435 \u043e \u043f\u043e\u0442\u0430\u043a\u0442\u043e\u0432\u043e\u0439 \u043c\u043e\u0434\u0435\u043b\u0438 \u0438 \u0442\u0440\u0430\u0441\u0441\u0430\u0445, \u043a\u043e\u0442\u043e\u0440\u044b\u0435 \u0431\u043e\u043b\u044c\u0448\u0435 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u0435\u043d\u044b \u0432 \u043a\u0440\u0443\u0433\u0430\u0445 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u0432. \u0412 \u043f\u0435\u0440\u0432\u043e\u0439 \u0447\u0430\u0441\u0442\u0438 \u044f \u0440\u0430\u0441\u0441\u043a\u0430\u0437\u0430\u043b, \u0447\u0442\u043e \u0442\u0430\u043a\u043e\u0435 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u044b \u0432\u043e\u043e\u0431\u0449\u0435, \u0430 \u0442\u0430\u043a\u0436\u0435 \u043e\u0431 \u0443\u0440\u043e\u0432\u043d\u044f\u0445 […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":87137,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[688],"tags":[],"class_list":["post-87136","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-administrirovanie"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t
![\"Computer](\"\/wp-content\/uploads\/2020\/07\/dbc7767cd563ce01b6145ac2e872d4c0.jpg\")