{"id":102428,"date":"2021-11-30T15:36:39","date_gmt":"2021-11-30T13:36:41","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/vortex-otkrytyj-gpgpu-na-baze-arhitektury-risc-v-sovmestimyj-s-opencl"},"modified":"2021-11-30T15:36:39","modified_gmt":"2021-11-30T13:36:41","slug":"vortex-otkrytyj-gpgpu-na-baze-arhitektury-risc-v-sovmestimyj-s-opencl","status":"publish","type":"post","link":"https:\/\/prohoster.info\/es\/blog\/news\/vortex-otkrytyj-gpgpu-na-baze-arhitektury-risc-v-sovmestimyj-s-opencl","title":{"rendered":"Vortex \u2014 GPU abierto basado en la arquitectura RISC-V, compatible con OpenCL","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"<p>Un grupo de investigadores del Instituto Tecnol\u00f3gico de Georgia est\u00e1 desarrollando el proyecto de investigaci\u00f3n Vortex, que ofrece GPGPU abierto basado en la arquitectura de conjunto de instrucciones RISC-V, dise\u00f1ado para realizar c\u00e1lculos paralelos utilizando la API OpenCL y el modelo de ejecuci\u00f3n SIMT (Single Instruction, Multiple Threads), as\u00ed como para llevar a cabo investigaciones en el campo de la gr\u00e1ficos 3D y el desarrollo de nuevas arquitecturas de GPU. El proyecto se encuentra a\u00fan en la etapa de prototipo, funcionando con FPGA. Los esquemas, descripciones de bloques de hardware en Verilog, simulador, controladores y la documentaci\u00f3n del proyecto se distribuyen bajo la licencia BSD.     <\/p>\n<p>En su forma actual, se proporciona una ISA RISC-V t\u00edpica, ampliada con algunas instrucciones adicionales necesarias para soportar funciones de GPU y gesti\u00f3n de flujos. Durante el desarrollo, los autores del proyecto trataron de minimizar los cambios en la arquitectura del conjunto de instrucciones RISC-V, utilizando, en lo posible, las instrucciones vectoriales ya existentes. Un enfoque similar se aplica tambi\u00e9n en el proyecto RV64X, que tambi\u00e9n desarrolla una GPU abierta basada en tecnolog\u00edas RISC-V.  <center><img decoding=\"async\" alt=\"Vortex - GPGPU abierto basado en la arquitectura RISC-V, compatible con OpenCL\" src=\"\/wp-content\/uploads\/2021\/11\/b28015da9f9188f87f402a8b14ee070b.jpg\" style=\"display:block;margin: 0 auto;\" \/><\/center>        <\/p>\n<p>Las capacidades de Vortex para el procesamiento gr\u00e1fico son bastante limitadas. Se ha anunciado el soporte de OpenGL ES en la plataforma Vortex, pero en el propio GPU solo se ha implementado la instrucci\u00f3n \u00abtex\u00bb para acelerar el procesamiento de texturas, que se ejecuta en el nivel del shader de fragmento. No hay un rasterizador integrado: toda la manipulaci\u00f3n de las operaciones geom\u00e9tricas se realiza en el CPU del sistema, y los primitivas b\u00e1sicas para puntos, l\u00edneas y tri\u00e1ngulos, as\u00ed como el procesamiento de fragmentos, profundidad y transparencia, se implementan utilizando el n\u00facleo de OpenCL.   <center><img decoding=\"async\" alt=\"Vortex - GPGPU abierto basado en la arquitectura RISC-V, compatible con OpenCL\" src=\"\/wp-content\/uploads\/2021\/11\/a12215387481ff353fb2fd4454c286da.jpg\" style=\"display:block;margin: 0 auto;\" \/><\/center>    <\/p>\n<p>En el futuro, se planea implementar extensiones espec\u00edficas para el procesamiento gr\u00e1fico en la ISA, a\u00f1adir soporte para las API CUDA y Vulkan, as\u00ed como extensiones para acelerar sistemas de aprendizaje autom\u00e1tico y an\u00e1lisis de datos. Se ofrece un conjunto de herramientas para el desarrollo de aplicaciones, que incluye variantes adaptadas para trabajar con Vortex de PoCL (compilador y runtime OpenCL), LLVM\/Clang, GCC y Binutils. Se admite la simulaci\u00f3n del funcionamiento del chip utilizando Verilator (simulador Verilog) y SimX (simulaci\u00f3n de software).    <center><img decoding=\"async\" alt=\"Vortex - GPGPU abierto basado en la arquitectura RISC-V, compatible con OpenCL\" src=\"\/wp-content\/uploads\/2021\/11\/d0b801f648a6863f190ec62c4a36fb6a.jpg\" style=\"display:block;margin: 0 auto;\" \/><\/center>    <\/p>\n<p>Caracter\u00edsticas principales de Vortex:  <\/p>\n<ul>\n<li class=\"l\"> Soporte para la arquitectura de conjunto de instrucciones RISC-V RV32IMF.\n<li class=\"l\"> Escalabilidad del chip a 64 n\u00facleos con cach\u00e9s opcionales L2 y L3.\n<li class=\"l\"> Cada n\u00facleo puede ejecutar 1024 hilos y operar a una frecuencia de 250 MHz.\n<li class=\"l\"> La potencia de c\u00e1lculo m\u00e1xima se estima en 128 Gflops, y el ancho de banda de memoria es de 16 GB\/s. La implementaci\u00f3n de 32 n\u00facleos, funcionando a 200 Mhz, basada en FPGA Altera Stratix 10, mostr\u00f3 un rendimiento de 25.6 GFlops.\n<li class=\"l\"> Soporte para el est\u00e1ndar OpenCL 1.2.\n<li class=\"l\"> Posibilidad de implementaci\u00f3n en FPGA Intel Arria 10 e Intel Stratix 10.    <\/ul>\n<p>Fuente: <a content=\"nofollow\" rel=\"nofollow\" href=\"https:\/\/www.opennet.ru\/opennews\/art.shtml?num=56253\">opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"<p>\u0413\u0440\u0443\u043f\u043f\u0430 \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u0435\u0439 \u0438\u0437 \u0422\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u043e\u0433\u043e \u0438\u043d\u0441\u0442\u0438\u0442\u0443\u0442\u0430 \u0414\u0436\u043e\u0440\u0434\u0436\u0438\u0438 \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u0442 \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u0441\u043a\u0438\u0439 \u043f\u0440\u043e\u0435\u043a\u0442 Vortex, \u043f\u0440\u0435\u0434\u043b\u0430\u0433\u0430\u044e\u0449\u0438\u0439 \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0439 GPGPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V, \u043d\u0430\u0446\u0435\u043b\u0435\u043d\u043d\u044b\u0439 \u043d\u0430 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u0435 \u043f\u0430\u0440\u0430\u043b\u043b\u0435\u043b\u044c\u043d\u044b\u0445 \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439 \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c API OpenCL \u0438 \u043c\u043e\u0434\u0435\u043b\u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f SIMT (Single Instruction, Multiple Threads), \u0430 \u0442\u0430\u043a\u0436\u0435 \u043d\u0430 \u043f\u0440\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u0435 \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0439 \u0432 \u043e\u0431\u043b\u0430\u0441\u0442\u0438 3D-\u0433\u0440\u0430\u0444\u0438\u043a\u0438 \u0438 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043d\u043e\u0432\u044b\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440 GPU. \u041f\u0440\u043e\u0435\u043a\u0442 \u043f\u043e\u043a\u0430 \u043d\u0430\u0445\u043e\u0434\u0438\u0442\u0441\u044f \u043d\u0430 \u0441\u0442\u0430\u0434\u0438\u0438 \u043f\u0440\u043e\u0442\u043e\u0442\u0438\u043f\u0430, [&hellip;]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":102429,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-102428","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.2 - aioseo.com -->\n\t<meta name=\"description\" content=\"\u0413\u0440\u0443\u043f\u043f\u0430 \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u0435\u0439 \u0438\u0437 \u0422\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u043e\u0433\u043e \u0438\u043d\u0441\u0442\u0438\u0442\u0443\u0442\u0430 \u0414\u0436\u043e\u0440\u0434\u0436\u0438\u0438 \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u0442 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