{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/es\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"El proyecto VeriGPU desarrolla un GPU abierto en el lenguaje Verilog","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

El proyecto VeriGPU tiene como objetivo crear una GPU abierta, desarrollada en el lenguaje de descripci\u00f3n y modelado de sistemas electr\u00f3nicos Verilog. Inicialmente, el proyecto se est\u00e1 desarrollando utilizando un simulador de Verilog, pero una vez que est\u00e9 listo, podr\u00e1 utilizarse para la producci\u00f3n de chips reales. Los progresos del proyecto se distribuyen bajo la licencia MIT. <\/p>\n

VeriGPU se posiciona como un procesador especializado (ASIC), optimizado para acelerar c\u00e1lculos relacionados con sistemas de aprendizaje autom\u00e1tico. Se menciona en los planes la garant\u00eda de compatibilidad con el marco de aprendizaje profundo PyTorch y la implementaci\u00f3n de la capacidad de desarrollar aplicaciones para VeriGPU utilizando la API HIP (Interfaz de C\u00f3mputo Heterog\u00e9neo). En el futuro, no se descarta la adici\u00f3n de soporte para otras API, como SYCL y NVIDIA CUDA. <\/p>\n

La GPU se desarrolla sobre la base de un conjunto de instrucciones RISC-V, pero la arquitectura interna final del conjunto de instrucciones de la GPU es d\u00e9bilmente compatible con la ISA RISC-V, ya que en situaciones donde el dise\u00f1o de la GPU no se ajusta a la representaci\u00f3n de RISC-V, no se prioriza mantener la compatibilidad con RISC-V. El desarrollo est\u00e1 enfocado en las capacidades necesarias para los sistemas de aprendizaje autom\u00e1tico, por lo que para reducir el tama\u00f1o y la complejidad de la matriz del chip, solo se utiliza el formato de c\u00e1lculos de punto flotante BF16 y solo est\u00e1n disponibles las operaciones de punto flotante demandadas para el aprendizaje autom\u00e1tico, como exp, log, tanh y sqrt. <\/p>\n

Entre los componentes ya disponibles se incluyen el controlador GPU, APU (Unidad de Procesamiento Acelerado) para operaciones aritm\u00e9ticas («+»,»-«,»\\\/»,»*»), un m\u00f3dulo para operaciones de punto flotante («+»,»*») y un m\u00f3dulo para la gesti\u00f3n de bifurcaciones. Para la creaci\u00f3n de aplicaciones se ofrece un ensamblador y soporte para la compilaci\u00f3n de c\u00f3digo en C++ basado en LLVM. Entre las capacidades planificadas se destacan la ejecuci\u00f3n paralela de instrucciones, el almacenamiento en cach\u00e9 de datos e instrucciones y las operaciones SIMT (Single instruction multiple thread).

\"El<\/center>
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Fuente: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103861,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103860","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47El proyecto VeriGPU desarrolla una GPU abierta en el lenguaje Verilog | ProHoster","description":"El proyecto VeriGPU tiene como objetivo crear una GPU abierta, desarrollada en el lenguaje de descripci\u00f3n y modelado de sistemas electr\u00f3nicos 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