{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/et\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"VeriGPU projekt arendab avatud GPU-d Verilog keeles","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

VeriGPU projekt on suunatud avatud GPU loomisele, kasutades elektrooniliste s\u00fcsteemide kirjeldamise ja modelleerimise keelt Verilog. Alguses arendatakse projekti kasutades Verilog simulaatorit, kuid p\u00e4rast valmimist saab seda kasutada reaalse chip'i tootmiseks. Projekti arengud levitatakse MIT litsentsi alusel. <\/p>\n

VeriGPU positsioneeritakse spetsialiseeritud protsessorina (ASIC), mis on optimeeritud masin\u00f5ppe s\u00fcsteemidega seotud arvutuste kiirendamiseks. Plaanides mainitakse \u00fchilduvuse tagamist s\u00fcvamasin\u00f5ppe raamistiku PyTorchiga ning v\u00f5imaluse rakenduste arendamiseks VeriGPU-le HIP (Heterogeneous-Compute Interface) API kasutamise kaudu. Tulevikus ei ole v\u00e4listatud ka teiste API-de, nagu SYCL ja NVIDIA CUDA, toe lisamine. <\/p>\n

GPU areneb RISC-V k\u00e4skude komplekti p\u00f5hjal, kuid l\u00f5plik sisemine arhitektuur on RISC-V ISA-ga halvasti \u00fchilduv, kuna olukordades, kus GPU projekteerimine ei vasta RISC-V ettekujutusele, ei seatud eesm\u00e4rgiks \u00fchilduvuse s\u00e4ilitamine RISC-V-ga. Arendust on keskendunud masin\u00f5ppe s\u00fcsteemide jaoks vajalikele v\u00f5imalustele, seet\u00f5ttu kasutatakse kiibi mahtude ja keerukuse v\u00e4hendamiseks ainult ujuva komaga arvutuste formaati BF16 ning on saadaval vaid masin\u00f5ppes n\u00f5utavad ujuva komaga toimingud, nagu exp, log, tanh ja sqrt. <\/p>\n

Saadaval olevatest komponentidest nimetatakse GPU kontrollerit, APU-d (Accelerated Processing Unit) t\u00e4isarvude operatsioonide jaoks («+»,»-«,»\\\/»,»*»), ujuva koma operatsioonide plokki («+»,»*») ja harunemisteenuste plokki. Rakenduste loomiseks pakutakse assemblerit ja C++ koodi kompileerimise tuge LLVM-i p\u00f5hjal. Plaanitavad funktsioonid h\u00f5lmavad k\u00e4skinstructsioonide paralleelset t\u00e4itmist, m\u00e4lutele ja k\u00e4skudele vahem\u00e4lu ning SIMT (Single instruction multiple thread) operatsioone.

\"VeriGPU<\/center>
\n
Allikas: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103861,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103860","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47VeriGPU projekt arendab avatud GPU-d Verilog keeles | ProHoster","description":"VeriGPU projekt on suunatud avatud GPU loomisele, kasutades elektrooniliste s\u00fcsteemide kirjeldamise ja modelleerimise keelt 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