{"id":56073,"date":"2020-02-04T00:00:00","date_gmt":"2020-02-03T21:00:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/blog_prohoster\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry"},"modified":"2020-02-18T14:04:16","modified_gmt":"2020-02-18T11:04:16","slug":"neizbezhnost-proniknoveniya-fpga-v-data-tsentry","status":"publish","type":"post","link":"https:\/\/prohoster.info\/et\/blog\/administrirovanie\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry","title":{"rendered":"FPGA sissetung on andmete keskustesse on v\u00e4ltimatu","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\"FPGA
\nFPGA jaoks programmeerimiseks ei pea olema kiibiarendaja, nagu ei pea olema C++ arendaja, et Java koodi kirjutada. Kuid m\u00f5lemal juhul v\u00f5ib see ilmselt olla kasulik.<\/p>\n

Nende kahe tehnoloogia, Java ja FPGA, kommertsialiseerimise eesm\u00e4rk on t\u00f5estada viimast v\u00e4idet. Head uudised FPGA jaoks \u2013 \u00f5ige abstraktsioonitasemete ja t\u00f6\u00f6riistakomplektide kasutamisega on viimase 35 aasta jooksul, alates programmeeritava loogikaseadmest, algoritmide ja andmevoogude loomine FPGA-dele muutunud kergemaks kui CPU, DSP, GPU v\u00f5i iga muu spetsiaalse ASIC-i kasutamine.<\/p>\n

Nende loomise m\u00e4rkimisv\u00e4\u00e4rne ajastus seisneb selles, et just siis, kui CPU ei saanud enam j\u00e4\u00e4da ainsaks arvutusmoduliks andmekeskustes<\/a> mitmete erinevate p\u00f5hjuste t\u00f5ttu, saavutas FPGA oma t\u00f5hususe, pakkudes k\u00f5rge j\u00f5udluse, madalat latentsust, v\u00f5rguv\u00f5imalusi ja m\u00e4lu \u2013 kaasaegsete FPGA SoC-de mitmekesised arvutusv\u00f5imaused, mis peaaegu kujutavad endast t\u00e4ielikke arvutuss\u00fcsteeme. Samuti sobivad FPGA h\u00e4sti ka teiste seadmetega h\u00fcbriids\u00fcsteemides ja meie arvates hakkavad nad alles leidma oma \u00f5igustatud kohta arvutuste hierarhias.
\n<\/a><\/noindex>
\nSeet\u00f5ttu korraldasime konverentsi The Next FPGA Platform San Jos\u00e9's 22. jaanuaril. Loomulikult on \u00fcks maailma peamisi FPGA tarnijaid ja selle valdkonna pioneere ettev\u00f5te Xilinx. Ivo Bolsens, ettev\u00f5tte Xilinx vanemdirektor ja tehniline direktor, esines konverentsil ettekandega ja jagas oma m\u00f5tteid selle kohta, kuidas Xilinx aitab luua muudetavaid arvutuss\u00fcsteeme andmekeskustele.<\/p>\n

S\u00fcsteemiarhitektide ja programmeerijate on kulunud piisavalt aega, et j\u00f5uda mitmekesise andmekeskuseni, kus on esindatud erinevat t\u00fc\u00fcpi arvutusv\u00f5imsus, mis lahendab arvutamise, salvestamise ja v\u00f5rgu korraldamise \u00fclesandeid. See n\u00e4ib olevat vajalik, kuna Moore'i seaduse j\u00e4rgimine erinevate CMOS-ide kasutamisel on \u00fcha raskem. Kunagi meie keel on endiselt seotud CPU-ga, ja me r\u00e4\u00e4gime endiselt \"rakenduste kiirusest\", pidades silmas programmide t\u00f6\u00f6 parendamist v\u00f5rreldes sellega, mida saab teha \u00fcksnes CPU-dega. Aja jooksul muutuvad andmekeskused arvutusv\u00f5imsuste, andmesalade ja nende k\u00f5igi \u00fchendavate protokollide kogumiks ning me naaseme selliste terminite juurde nagu \"arvutused\" ja \"rakendused\". H\u00fcbriidarvutused saavad olema sama normaalsed kui t\u00e4nased \"pilveteenused\", mis p\u00f5hinevad tavalisel v\u00f5i virtuaalmasinate<\/a>, ja mingil hetkel kasutame lihtsalt s\u00f5na \"arvutused\", et kirjeldada nende t\u00f6\u00f6d. Mingil hetkel \u2013 ja t\u00f5en\u00e4oliselt aitavad sellele ajastule aktiivselt kaasa FPGA-d \u2013 nimetame seda j\u00e4lle andmete t\u00f6\u00f6tlemiseks.<\/p>\n

FPGA-de juurutamiseks andmekeskustesse on vajalik muuta m\u00f5tteviisi. \"M\u00f5eldes t\u00e4nap\u00e4evaste rakenduste kiirendamise viisidele, tuleb s\u00fc\u00fcvida nende alusp\u00f5him\u00f5tetesse, kuidas need t\u00e4idetakse, milliseid ressursse kasutatakse, millele kulub aega, \"selgitab Bolesens. \u2013 On vaja uurida \u00fcldprobleemi, mida \u00fcritate lahendada. Paljud rakendused, mis t\u00e4nap\u00e4eval andmekeskustes t\u00f6\u00f6tavad, skaleeruvad, haarates suures koguses ressursse. V\u00f5tame n\u00e4iteks masin\u00f5ppe, mis kasutab tohutult palju arvutusnode. Kuid r\u00e4\u00e4kides kiirusest, tuleb m\u00f5elda mitte ainult arvutuste kiirendamisele, vaid ka infrastruktuuri kiirendamisele.\"<\/p>\n

N\u00e4iteks nende masin\u00f5ppe operatsioonide puhul, mida Bolesens on praktiliselt uurinud, kulub umbes 50% ajast andmete edastamiseks edasi-tagasi hajutatud arvutusv\u00f5imsuste vahel ja ainult \u00fclej\u00e4\u00e4nud pool aega kulub arvutustele endile.<\/p>\n

Just here, it seems to me, FPGA can help, as we can optimize both the computational aspects and the data transmission aspects for the application. And we can do this at the level of the overall infrastructure and at the chip level. This is one of the great advantages of FPGA, allowing for the creation of communication networks tailored to the specific needs of the application. Observing typical patterns of data movement in tasks related to artificial intelligence, I don't see the need for a complex architecture based on switches. A network with high data flow can be built. The same applies to neural network training tasks \u2013 a mesh network can be constructed with packet sizes adapting to the specific task. Using FPGA, data transmission protocols and circuit topology can be scaled and adapted very precisely for a specific application. And in the case of machine learning, it is also clear that we do not need double-precision floating-point numbers, and we can adjust this as well.<\/p>\n

The difference between FPGA and CPU or specialized ASIC is that the latter are programmed during production, and after that, you cannot reconsider the types of computed data or computed elements, or the nature of the data flow through the device. FPGAs allow you to rethink if the operating conditions change.<\/p>\n

In the past, this advantage came at a high cost when programming for FPGA was not for the faint-hearted. It is necessary to open FPGA compilers so that they integrate better with the tools used by programmers to create applications with parallel computations for CPU in C, C++, or Python, and to delegate part of the work to libraries that accelerate procedures on FPGA. This is precisely what the Vitis machine learning stack does, which underlies machine learning platforms like Caffe and TensorFlow, and has libraries for executing standard AI models or adding FPGA capabilities to tasks such as video transcoding, object recognition in video, data analysis, financial risk management, and any third-party libraries.<\/p>\n

See kontseptsioon ei erine oluliselt Nvidia CUDA projektist, mis k\u00e4ivitus k\u00fcmme aastat tagasi ja suunab paralleelsed arvutused GPU-kiirenditele, samuti AMD ROCm t\u00f6\u00f6riistakomplektist v\u00f5i Inteli OneAPI projektist, mis lubab t\u00f6\u00f6tada erinevate CPU-de, GPU-de ja FPGA-dega.<\/p>\n

K\u00fcsimus on vaid selles, kuidas k\u00f5ik need t\u00f6\u00f6riistad omavahel seostuvad, et iga\u00fcks saaks programmeerida arvutusv\u00f5imet vastavalt oma soovidele. See on oluline, kuna FPGA-d on muutunud keerukamaks, palju keerukamaks kui \u00fckski olemasolev CPU. Neid toodetakse k\u00f5ige arenenumate tehnoloogiliste protsesside abil ja k\u00f5ige kaasaegsemaid kiibi pakendamise tehnoloogiaid kasutades. Nad leiavad oma ni\u0161i, kuna me ei saa enam raisata aega, raha, energiat ja intelligentsust \u2013 k\u00f5ik need on liiga kallid ressursid.<\/p>\n

\u201eFPGA pakuvad tehnoloogilisi eeliseid,\u201d \u00fctleb Bolsens. \u201eJa see ei ole lihtsalt tavaline reklaam kohandatavuse ja \u00fcmberseadmise kohta. K\u00f5igis olulistes rakendustes \u2013 masin\u00f5pe, graafide anal\u00fc\u00fcs, k\u00f5rge sagedusega kauplemine ja nii edasi \u2013 on neil v\u00f5imalus kohandada mitte ainult andmete edastusviisi, vaid ka m\u00e4lu arhitektuuri \u2013 kuidas andmed liikuvad kiibi sees. Ja FPGA-des on oluliselt rohkem m\u00e4lu kui teistes seadmetes. Samuti tuleb arvestada, et kui \u00fclesanne ei mahu \u00fchte FPGA-sse, saab seda skaleerida mitmele kiibile, v\u00e4ltides neid puudusi, millega kokku puutute, skaleerides \u00fclesandeid mitme CPU v\u00f5i GPU peale.\u201c
\n
Allikas: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041d\u0435 \u043d\u0443\u0436\u043d\u043e \u0431\u044b\u0442\u044c \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u043c \u0447\u0438\u043f\u043e\u0432, \u0447\u0442\u043e\u0431\u044b \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0434\u043b\u044f FPGA, \u043a\u0430\u043a \u043d\u0435 \u043d\u0443\u0436\u043d\u043e \u0431\u044b\u0442\u044c \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0441\u0442\u043e\u043c \u043d\u0430 \u0421++, \u0447\u0442\u043e\u0431\u044b \u043f\u0438\u0441\u0430\u0442\u044c \u043a\u043e\u0434 \u043d\u0430 Java. \u041e\u0434\u043d\u0430\u043a\u043e \u0432 \u043e\u0431\u043e\u0438\u0445 \u0441\u043b\u0443\u0447\u0430\u044f\u0445, \u0432\u0435\u0440\u043e\u044f\u0442\u043d\u043e, \u044d\u0442\u043e \u0431\u0443\u0434\u0435\u0442 \u043d\u0435 \u043b\u0438\u0448\u043d\u0438\u043c. \u0426\u0435\u043b\u044c \u043a\u043e\u043c\u043c\u0435\u0440\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043e\u0431\u0435\u0438\u0445 \u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0439, Java \u0438 FPGA, \u0432 \u0442\u043e\u043c, \u0447\u0442\u043e\u0431\u044b \u043e\u043f\u0440\u043e\u0432\u0435\u0440\u0433\u043d\u0443\u0442\u044c \u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0435\u0435 \u0437\u0430\u044f\u0432\u043b\u0435\u043d\u0438\u0435. \u0425\u043e\u0440\u043e\u0448\u0438\u0435 \u043d\u043e\u0432\u043e\u0441\u0442\u0438 \u0434\u043b\u044f FPGA \u2013 \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u043f\u043e\u0434\u0445\u043e\u0434\u044f\u0449\u0438\u0445 \u0443\u0440\u043e\u0432\u043d\u0435\u0439 \u0430\u0431\u0441\u0442\u0440\u0430\u043a\u0446\u0438\u0438 \u0438 \u043d\u0430\u0431\u043e\u0440\u0430 […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":56074,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[688],"tags":[],"class_list":["post-56073","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-administrirovanie"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47FPGA sisenemise v\u00e4ltimatus andmekeskustesse | ProHoster","description":"Tihedust ei pea olema kiibiarendaja, et.","canonical_url":"https:\/\/prohoster.info\/et\/blog\/administrirovanie\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry","robots":"max-image-preview:large","keywords":"","webmasterTools":{"miscellaneous":""},"schema":null,"og:locale":"et_EE","og:site_name":"ProHoster | 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