{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/fr\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"Le projet VeriGPU d\u00e9veloppe un GPU ouvert en langage Verilog","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Le projet VeriGPU vise \u00e0 cr\u00e9er un GPU ouvert, d\u00e9velopp\u00e9 dans le langage de description et de mod\u00e9lisation des syst\u00e8mes \u00e9lectroniques Verilog. Initialement, le projet est d\u00e9velopp\u00e9 \u00e0 l'aide d'un simulateur Verilog, mais une fois pr\u00eat, il pourra \u00eatre utilis\u00e9 pour la fabrication de puces r\u00e9elles. Les contributions du projet sont diffus\u00e9es sous licence MIT. <\/p>\n

VeriGPU est positionn\u00e9 comme un processeur sp\u00e9cialis\u00e9 (ASIC), optimis\u00e9 pour acc\u00e9l\u00e9rer les calculs li\u00e9s aux syst\u00e8mes d'apprentissage automatique. Les plans mentionnent d'assurer la compatibilit\u00e9 avec le cadre d'apprentissage automatique profond PyTorch et la mise en \u0153uvre d'applications pour VeriGPU en utilisant l'API HIP (Heterogeneous-Compute Interface). \u00c0 l'avenir, l'ajout de support pour d'autres API, telles que SYCL et NVIDIA CUDA, n'est pas exclu. <\/p>\n

Le GPU est d\u00e9velopp\u00e9 sur la base d'un ensemble d'instructions RISC-V, mais l'architecture interne finale de l'ensemble d'instructions GPU est faiblement compatible avec RISC-V ISA, car dans les situations o\u00f9 la conception du GPU ne tient pas compte de la repr\u00e9sentation RISC-V, il n'est pas pr\u00e9vu de maintenir la compatibilit\u00e9 avec RISC-V. Le d\u00e9veloppement est ax\u00e9 sur les capacit\u00e9s n\u00e9cessaires pour les syst\u00e8mes d'apprentissage automatique, donc pour r\u00e9duire la taille et la complexit\u00e9 de la matrice de puce, seul le format de calcul \u00e0 virgule flottante BF16 est utilis\u00e9 et seules les op\u00e9rations \u00e0 virgule flottante requises pour l'apprentissage automatique, telles que exp, log, tanh et sqrt, sont disponibles. <\/p>\n

Parmi les composants d\u00e9j\u00e0 disponibles, on trouve le contr\u00f4leur GPU, l'APU (Unit\u00e9 de traitement acc\u00e9l\u00e9r\u00e9) pour les op\u00e9rations arithm\u00e9tiques («+»,»-«,»\\\/»,»*»), le bloc pour les op\u00e9rations \u00e0 virgule flottante («+»,»*») et le bloc d'assistance \u00e0 la branche. Pour le d\u00e9veloppement d'applications, un assembleur est propos\u00e9 ainsi qu'un support de compilation du code en C++ bas\u00e9 sur LLVM. Parmi les fonctionnalit\u00e9s pr\u00e9vues, on peut mentionner l'ex\u00e9cution parall\u00e8le des instructions, le caching de la m\u00e9moire des donn\u00e9es et des instructions, ainsi que les op\u00e9rations SIMT (Single Instruction Multiple Threads).

\"Le<\/center>
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Source : opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. 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