Kamar yadda muka sani, sauyi zuwa fasahar tsari na 3 nm za ta kasance tare da canji zuwa sabon tsarin gine-ginen transistor. A cikin sharuddan Samsung, alal misali, waɗannan za su zama transistor MBCFET (Multi Bridge Channel FET), wanda tashar transistor za ta yi kama da tashoshi da yawa da ke saman juna a cikin nau'in nanopages, kewaye da kofa ta kowane bangare (don ƙarin cikakkun bayanai). , gani ).
A cewar masu haɓakawa daga cibiyar Imec na Belgium, wannan ci gaba ne, amma ba manufa ba, tsarin transistor ta amfani da ƙofofin FinFET a tsaye. Mafi dacewa don hanyoyin fasaha tare da ma'auni na kashi ƙasa da 3 nm , wanda Belgians suka gabatar.
Imec ya haɓaka transistor tare da raba shafuka ko Forksheet. Waɗannan su ne nanopages na tsaye iri ɗaya da tashoshi na transistor, amma an raba su ta hanyar dielectric a tsaye. A gefe ɗaya na dielectric, an halicci transistor tare da tashar n-tashar, a daya, tare da tashar p-tashar. Kuma dukansu biyun suna kewaye da suttura na gama-gari a cikin hanyar haƙarƙari a tsaye.
Rage nisan kan-chip tsakanin transistor tare da gudanarwa daban-daban wani babban ƙalubale ne don ci gaba da raguwar tsari. Simulators na TCAD sun tabbatar da cewa transistor mai raba shafi zai samar da raguwar kashi 20 cikin 4,3 a yankin mutu. Gabaɗaya, sabon tsarin gine-ginen transistor zai rage daidaitattun tsayin tantanin halitta zuwa waƙoƙi XNUMX. Tantanin halitta zai zama mai sauƙi, wanda kuma ya shafi kera na'urar ƙwaƙwalwar ajiyar SRAM.
Sauƙaƙan sauyi daga nanopage transistor zuwa transistor nanopage tsaga zai samar da haɓaka 10% a cikin aiki yayin kiyaye amfani, ko raguwar 24% na amfani ba tare da samun aiki ba. Kwaikwayo don tsarin 2nm ya nuna cewa tantanin halitta SRAM ta amfani da keɓaɓɓen nanopages zai samar da haɗin rage yanki da haɓaka aikin har zuwa 30% tare da p- da n-junction tazara har zuwa 8 nm.
source: 3dnews.ru