Kamfanin SiFive, wanda masu kirkiro na RISC-V suka kafa tsarin gine-gine kuma a lokaci guda suna shirya samfurin farko na na'ura mai sarrafa RISC-V, ya gabatar da sabon RISC-V CPU core a cikin SiFive Performance line, wanda shine 50. % sauri fiye da farkon P550 na sama na baya kuma ya fi girma a cikin aikin ARM Cortex-A78, mafi ƙarfin sarrafawa dangane da gine-ginen ARM. SoCs dangane da sabon cibiya an yi niyya ne da farko ga tsarin uwar garken da wuraren aiki, amma kuma yana yiwuwa a ƙirƙiri ruɓaɓɓen juzu'ai don wayar hannu da na'urorin da aka haɗa.
An bayyana cewa, idan aka kwatanta da P550, sabon SiFive processor core ya ƙunshi 16 MB na L3 cache maimakon 4 MB, yana iya haɗawa har zuwa cores 16 a cikin guntu ɗaya maimakon 4, yana aiki a mitar har zuwa 3.5 GHz maimakon 2.4. 5 GHz, tana goyan bayan ƙwaƙwalwar DDR5.0 da bas ɗin PCI-Express 550. Babban tsarin gine-ginen sabon cibiya yana kusa da PXNUMX kuma shima yana da tsari a yanayi, yana ba da damar ƙarin tubalan tare da ƙwararrun masu haɓakawa ko GPUs don ƙarawa zuwa SoC. Ana shirin buga cikakkun bayanai a watan Disamba, kuma za a buga bayanan RTL da ke shirye FPGA a shekara mai zuwa.
RISC-V yana ba da tsarin koyarwar injin buɗewa da sassauƙa wanda ke ba ku damar ƙirƙirar SoCs da microprocessors gabaɗaya don aikace-aikacen sabani, ba tare da buƙatar sarauta ko sanya sharuɗɗan amfani ba. A halin yanzu, dangane da ƙayyadaddun RISC-V, bambance-bambancen bambance-bambancen microprocessor 2.0, dandamali 111, 31 SoCs da allunan shirye-shiryen 12 suna haɓaka ta kamfanoni daban-daban da al'ummomi a ƙarƙashin lasisi daban-daban na kyauta (BSD, MIT, Apache 12).
source: budenet.ru