Kamar yadda kuka sani, mai kula da hanyar sadarwa ta PCI Express, ƙungiyar PCI-SIG ta masana'antu, tana cikin gaggawa don gyara dogon laka a bayan jadawalin don kawo kasuwa da sabon sigar bas ɗin PCI Express ta amfani da takamaiman sigar 5.0. An amince da sigar ƙarshe na ƙayyadaddun bayanai na PCIe 5.0 da wannan , kuma a cikin sabuwar shekara na'urorin tare da goyon baya ga sabunta bas ya kamata su bayyana a kasuwa. Bari mu tunatar da ku cewa, idan aka kwatanta da PCIe 4.0, saurin canja wuri tare da layin PCIe 5.0 zai ninka zuwa 32 gigatransactions a sakan daya (32 GT/s).
Ƙayyadaddun ƙayyadaddun bayanai sune ƙayyadaddun bayanai, amma don aiwatar da aikace-aikacen sabon ƙirar, ana buƙatar silicon aiki da tubalan don ba da lasisi ga masu haɓaka masu sarrafawa na ɓangare na uku. Ɗaya daga cikin waɗannan shawarwarin jiya da yau a wani taro a Taipei kamfanonin Astera Labs, Synopsys da Intel. An yi iƙirarin cewa wannan shine cikakken bayani na farko wanda ke da cikakkiyar shiri don aiwatarwa a samarwa da kuma lasisi.
Dandalin da aka nuna a Taiwan yana amfani da guntu na farko na Intel, Synopsys DesignWare mai kula da layin jiki na PCIe 5.0 na kamfanin, wanda za'a iya siya a ƙarƙashin lasisi, da kuma masu ritaya daga Astera Labs. Masu ritaya su ne kwakwalwan kwamfuta waɗanda ke dawo da mutuncin agogon bugun jini a gaban tsangwama ko a cikin sigina mai rauni.
Kamar yadda kuke tsammani, yayin da saurin watsa bayanai kan layi ɗaya ke ƙaruwa, amincin siginar yana ƙara raguwa yayin da layin sadarwa ke ƙara tsayi. Alal misali, bisa ga ƙayyadaddun layin PCIe 4.0, kewayon watsawa ba tare da amfani da masu haɗawa a kan layin ba shine kawai 30 cm. Don layin PCIe 5.0, wannan nisa zai zama ya fi guntu kuma ko da a irin wannan nisa wajibi ne a haɗa shi. masu ritaya a cikin da'ira mai sarrafawa. Astera Labs ya gudanar da haɓaka masu ritaya waɗanda za su iya aiki duka a cikin ƙirar PCIe 4.0 kuma a matsayin ɓangare na ƙirar PCIe 5.0, wanda aka nuna a taron.
source: 3dnews.ru