An buga sabon bugu na aikin Vortex, yana haɓaka GPGPU mai buɗewa dangane da tsarin tsarin koyarwa na RISC-V, wanda aka ƙera don yin lissafin layi ɗaya ta amfani da OpenCL API da kuma tsarin aiwatar da SIMT (Umar guda ɗaya, Zaren Multiple). Hakanan za'a iya amfani da aikin a cikin bincike a fagen zane-zane na 3D da haɓaka sabbin gine-ginen GPU. Ana rarraba tsare-tsare, kwatancen tubalan kayan masarufi a cikin yaren Verilog, na'urar kwaikwayo, direbobi da takaddun ƙira masu rakiyar ƙarƙashin lasisin Apache 2.0.
Jigon GPGPU shine RISC-V ISA na gabaɗaya, wanda aka haɓaka tare da wasu ƙarin umarni da ake buƙata don tallafawa aikin GPU da sarrafa zaren. A lokaci guda, canje-canje a cikin tsarin tsarin koyarwa na RISC-V ana kiyaye su zuwa mafi ƙanƙanta kuma, duk lokacin da zai yiwu, ana amfani da umarnin vector data kasance. Ana amfani da irin wannan hanyar a cikin aikin RV64X, wanda kuma yana haɓaka GPU mai buɗewa dangane da fasahar RISC-V.
Babban fasali na Vortex:
- Yana goyan bayan 32- da 64-bit RISC-V umarni saitin gine-gine RV32IMF da RV64IMAFD.
- Ƙimar ƙira mai ƙima, tubalan ɗawainiya (warps) da zaren zare.
- Adadin daidaitacce na ALUs, FPUs, LSUs da SFUs akan ainihin.
- Faɗin batun bututun mai daidaitacce.
- Ƙwaƙwalwar ajiya na zaɓi da L1, L2 da L3 caches.
- OpenCL 1.2 goyon bayan ƙayyadaddun bayanai.
- Yiwuwar aiwatarwa bisa FPGA Altera Arria 10, Altera Stratix 10, Xilinx Alveo U50, U250, U280 da Xilinx Versal VCK5000.
- Babban umarni: "tex" don hanzarta sarrafa rubutu, vx_rast don sarrafa rasterization, vx_rop don sarrafa gutsuttsura, zurfin da bayyana gaskiya, vx_imadd don yin ninka da ƙara ayyuka, vx_wspawn, vx_tmc da vx_bar don kunna gefuna na umarni da wavefronts, saitin zaren. wanda aka kashe a layi daya ta Injin SIMD), vx_split da vx_join.
- Ana aiwatar da tallafi don wakilcin tsaka-tsaki na shaders na SPIR-V ta hanyar fassara zuwa OpenCL.
- Don haɓaka aikace-aikacen, ana ba da kayan aikin kayan aiki, gami da bambance-bambancen PoCL (mai tarawa da lokacin aiki OpenCL), LLVM/Clang, GCC da Binutils waɗanda aka daidaita don aiki tare da Vortex.
- Ana goyan bayan simintin Chip ta amfani da Verilator (Verilog na'urar kwaikwayo), RTLSIM (RTL simulation) da SimX (kwaikwaiyon software).
Don zane-zane dangane da fasahar Vortex, ana haɓaka buɗaɗɗen GPU Skybox, yana tallafawa API ɗin Vulkan graphics. Prototype na SkyBox, wanda aka kirkireshi a kan Alterera Stratix 10 FPGA da ciki har da 32 GigApixels na biyu (512 Gigatrana), ya sanya hakan zai yiwu a cimma wani matsayi na biyu (230 Gigabbans na biyu (3.7 GigatranSais An lura cewa wannan shine farkon buɗaɗɗen GPU tare da aiwatar da software da kayan aikin da ke tallafawa Vulkan.
Daga cikin canje-canje a cikin Vortex 2.1:
- Ƙara spawn_taskgroups API don ƙaddamar da kernels masu amfani da ƙwaƙwalwar gida da goyan bayan saitin ƙwaƙwalwar ajiya.
- An gabatar da sabon tsawaita don ƙirƙirar kwayayen binaryar da za a sake matsuwa.
- Ƙara vx_mem_reserve, vx_mem_access da vx_mem_address kira zuwa API sarrafa ƙwaƙwalwar ajiya.
- An ƙara sabon lokacin gudu API vx_check_occupancy.
- An ƙara wani zaɓi zuwa direban GPU don gudanar da gwaje-gwajen OpenCL akan GPU na gida.
- An ƙara gwaje-gwajen OpenCL waɗanda ke amfani da ƙwaƙwalwar gida (psum, sgemm2, sgemm3).
- Ƙarin bugu na libc da ɗakunan karatu na librt waɗanda aka dace musamman don Vortex.
- Ƙarin tallafi don haɗa tubalan ƙwaƙƙwarar kyauta na kusa (haɗin ƙwaƙwalwar ajiya).
- An inganta microarchitecture.
- An ƙara sabon rubutun gini wanda ke raba fayilolin tushen daga tsarin ginin ginin.
source: budenet.ru
