Vortex 3.0, tushen budewa GPGPU dangane da gine-ginen RISC-V, an buga

Aikin Vortex 3.0, wanda ke haɓaka GPGPU mai buɗewa bisa tsarin saitin umarni na RISC-V kuma an tsara shi don lissafi mai layi ɗaya ta amfani da OpenCL API da samfurin aiwatarwa na SIMT (Gudanarwa Guda ɗaya, Zaren da Yawa), yanzu yana samuwa. Hakanan ana iya amfani da aikin don binciken zane-zane na 3D da haɓaka sabbin gine-ginen GPU. An rarraba zane-zane, bayanin tubalan kayan aiki a cikin Verilog, na'urar kwaikwayo, direbobi, da takaddun ƙira masu rakiyar a ƙarƙashin lasisin Apache 2.0.

GPGPU ya dogara ne akan daidaitaccen RISC-V ISA, wanda aka faɗaɗa tare da ƙarin umarni don tallafawa fasalulluka na GPU da sarrafa zare. Ana kiyaye canje-canje ga tsarin saitin umarni na RISC-V zuwa mafi ƙanƙanta, kuma ana amfani da umarnin vector na yanzu duk lokacin da zai yiwu. Ƙarin umarni sun haɗa da: "tex" don hanzarta sarrafa rubutu; vx_rast don sarrafa rasterization; vx_rop don sarrafa guntu, zurfi, da bayyanawa; vx_imadd don ayyukan ninka-da-ƙara; vx_wspawn, vx_split, vx_join, vx_tmc, da vx_bar don kunna ƙungiyoyin zare (wavefronts) waɗanda aka aiwatar a layi ɗaya ta hanyar SIMD Engine.

GPGPU da ake haɓakawa yana goyan bayan tsarin saitin umarni na RISC-V RV32IMF da RV64IMAFD 32 da 64-bit kuma yana iya haɗawa da ƙwaƙwalwar ajiya da aka raba, ma'ajiyar L1, L2, da L3, da adadin ma'ajiyar tsakiya, warps, da zare mai daidaitawa. Kowace ma'ajiyar tsakiya kuma tana iya haɗawa da adadin ALUs, FPUs, LSUs, da SFUs masu daidaitawa. Ana iya amfani da Xilinx da Altera FPGAs don yin samfuri, kuma ana iya amfani da Verilator (Verilog simulator), RTLSIM (RTL simulation), da SimX (software simulating) don kwaikwayon guntu.

Don haɓaka aikace-aikace, ana bayar da kayan aiki, gami da nau'ikan PoCL (mai haɗa OpenCL da lokacin aiki), LLVM/Clang, GCC, da Binutils waɗanda Vortex ya daidaita. Aikin yana goyan bayan ƙayyadaddun OpenCL 1.2 kuma yana aiwatar da tallafi don wakilcin SPIR-V na matsakaiciyar shaders ta hanyar fassara zuwa OpenCL.

Canje-canje a cikin Vortex 3.0 sun haɗa da:

• An ƙara tarin zane-zane na kayan aiki, gami da tubalan don rasterization, taswirar rubutu, da haɗakar fitarwa (OM). An ƙirƙiri wani direban Vulkan, vortexpipe, don Mesa bisa ga tsarin zane-zane da aka aiwatar da kuma rasterizer na software na lavapipe.
• An faɗaɗa ƙarfin Tensor Core, wanda aka tsara don hanzarta aiwatar da samfuran koyon injina, ta hanyar aiwatar da tallafi ga tsarin sparsity don matse matrices na nauyi.
• An aiwatar da aikin WGMMA (warpgroup-level matrix multiplication) don ninka matrix a cikin yanayin asynchronous.
• An ƙara injin DXA (Acceleration Transfer Data) don hanzarta canja wurin bayanai daga ƙwaƙwalwar ajiya ta duniya zuwa ta gida.
• An aiwatar da sabon tsarin gine-gine bisa ga na'urar sarrafa umarni (CP) da kuma na'urar tsara kayan aiki na kwamfutocin tsakiya (KMU - Kernel Management Unit), wanda ke ba da damar aika zaren kwamfuta zuwa gefen guntu.
• An gabatar da sabon ɗakin karatu na lokacin aiki wanda ke aiki a yanayin da ba ya toshewa kuma yana samar da abubuwan da ke fassara zuwa umarnin kayan aiki da aka aiwatar ba tare da haɗin kai ba. Ana tallafawa layuka, abubuwan da suka faru, kayayyaki, da daidaitawa bisa ga shingen asynchronous tare da ma'anar isowa/jira/taron.
• An ƙara tallafi ga Umarnin Gajerun RISC-V (RVC).
• An aiwatar da tallafin kayan aiki don ayyukan atomic (Atomic na Hardware).
• An sake fasalin FPU gaba ɗaya kuma an gabatar da sabbin tubalan multiplier (Wallace-tree, Folded-radix) da adder (Kogge-Stone).
• An ƙara tarin ƙwaƙwalwar ajiya ta kama-da-wane bisa ga na'urar sarrafa ƙwaƙwalwa (MMU) tare da tallafi ga tsarin adireshin kama-da-wane na SV32 mai bit 32.
• Tallafi ga tsawaita aikin RISC-V Zicond tare da aiwatar da ayyukan da aka tsara.
• Haɗaɗɗen ƙofar agogo.
• An aiwatar da tallafi ga harshen HIP (Heterogeneous Interface for Portability) ta hanyar tsarin chipStar, wanda ke fassara HIP zuwa SPIR-V.
• An samar da cikakken haɗin kai tare da na'urar kwaikwayo ta GEM5, kuma an ƙara tallafi ga na'urar kwaikwayo ta SimX akan tsarin TLM (Tsarin Tsarin Canja-Matsayi).
• An ƙara tallafi ga kayan aikin Synopsys da Yosys don haɗa dabaru don kera guntu, da kuma tallafi don amfani da ɗakunan karatu na ASAP7 (7nm), SAED14 (14nm), da NanGate (15nm) na daidaitattun kayan aiki.
• An sabunta tsarin kayan aikin tunani zuwa LLVM 20 da POCL 7.0.

source: budenet.ru