E like me kā mākou ʻike, ʻo ka hoʻololi ʻana i kahi ʻenehana kaʻina hana 3 nm e hele pū me kahi hoʻololi i kahi hoʻolālā transistor hou. Ma nā huaʻōlelo Samsung, no ka laʻana, ʻo ia nā transistors MBCFET (Multi Bridge Channel FET), kahi e nānā ai ke kahawai transistor e like me nā kaha he nui ma luna o kekahi i ke ʻano o nā nanopages, i hoʻopuni ʻia ma nā ʻaoʻao a pau e kahi puka (no nā kikoʻī hou aku. , nana ).
Wahi a nā mea hoʻomohala mai ka Belgian center Imec, he holomua kēia, akā ʻaʻole kūpono, ka hoʻolālā transistor me ka hoʻohana ʻana i nā puka FinFET vertical. He kūpono no nā kaʻina hana ʻenehana me nā unahi element ma lalo o 3 nm , i manaoia e na Belgians.
Ua hoʻomohala ʻo Imec i kahi transistor me nā ʻaoʻao māhele a i ʻole Forksheet. ʻO kēia nā nanopages kūpaʻa like me nā kahawai transistor, akā hoʻokaʻawale ʻia e kahi dielectric vertical. Ma kekahiʻaoʻao o ka dielectric, ua hanaʻia kahi transistor me kahi n-channel, ma kekahiʻaoʻao, me kahi p-channel. A ua hoʻopuni ʻia lāua ʻelua e kahi pani maʻamau i ke ʻano o ka iwi ʻaoʻao.
ʻO ka hoʻemi ʻana i ka mamao ma-chip ma waena o nā transistors me nā conductivities ʻē aʻe kekahi pilikia nui no ka hoʻohaʻahaʻa hou ʻana. Ua hōʻoia ʻo TCAD simulation e hāʻawi ka transistor māhele ʻaoʻao i kahi hōʻemi 20 pakeneka o ka wahi make. Ma keʻano laulā, e hoʻemi ka hoʻolālā transistor hou i ke kiʻekiʻe o ke kelepona logic maʻamau i 4,3 tracks. E maʻalahi ke kelepona, e pili pū ana i ka hana ʻana o ka cell memory SRAM.
ʻO kahi hoʻololi maʻalahi mai kahi transistor nanopage i kahi transistor nanopage split e hāʻawi i ka hoʻonui ʻana o 10% i ka hana ʻoiai e mālama ana i ka hoʻohana ʻana, a i ʻole he 24% hōʻemi i ka ʻai me ka loaʻa ʻole o ka hana. Hōʻike nā hoʻohālikelike no ke kaʻina hana 2nm e hāʻawi ka SRAM cell e hoʻohana ana i nā nanopage i hoʻokaʻawale ʻia i ka hoʻemi ʻana o ka wahi a me ka hoʻomaikaʻi ʻana i ka hana a hiki i 30% me ka p- a me n-junction spacing a hiki i 8 nm.
Source: 3dnews.ru