ʻO ka hui SiFive, i hoʻokumu ʻia e nā mea hana o ka RISC-V instruction set architecture a i ka manawa hoʻokahi e hoʻomākaukau ana i ka prototype mua o kahi kaʻina hana RISC-V, ua hoʻokomo i kahi core RISC-V CPU hou i ka laina SiFive Performance, ʻo ia ka 50 % ʻoi aku ka wikiwiki ma mua o ka P550 core top-end mua a ʻoi aku ka maikaʻi ma ka hana ARM Cortex-A78, ka mea hana ikaika loa e pili ana i ka hoʻolālā ARM. ʻO nā SoC i hoʻokumu ʻia i ke kumu hou e kuhikuhi nui ʻia i nā ʻōnaehana server a me nā keʻena hana, akā hiki nō ke hana i nā mana i hoʻokaʻawale ʻia no nā polokalamu kelepona a hoʻokomo ʻia.
Ua ʻōlelo ʻia, i hoʻohālikelike ʻia me ka P550, ʻo ka SiFive processor core hou he 16 MB o L3 cache ma kahi o 4 MB, hiki ke hui pū ʻia a hiki i 16 cores i hoʻokahi pahu ma kahi o 4, e hana ana ma ke alapine a hiki i 3.5 GHz ma kahi o 2.4 GHz, kākoʻo i ka hoʻomanaʻo DDR5 a me ka pahi ʻo PCI-Express 5.0. ʻO ka hoʻolālā maʻamau o ke kumu hou e pili kokoke ana i ka P550 a he modular nō hoʻi i ke ʻano, e ʻae ana i nā poloka hou me nā accelerators kūikawā a i ʻole GPU e hoʻohui ʻia i ka SoC. Hoʻolālā ʻia nā kikoʻī e paʻi ʻia i Dekemaba, a e paʻi ʻia ka ʻikepili FPGA-ready RTL i ka makahiki aʻe.
Hāʻawi ʻo RISC-V i kahi ʻōnaehana aʻoaʻo mīkini hāmama a maʻalahi e hiki ai iā ʻoe ke hana i nā SoCs a me nā microprocessors hāmama loa no nā noi arbitrary, me ka ʻole o ke koi ʻana i nā royalties a i ʻole ke kau ʻana i nā kūlana ma ka hoʻohana. I kēia manawa, e pili ana i ka kikoʻī RISC-V, 2.0 mau ʻano like ʻole o nā microprocessor cores, 111 platforms, 31 SoCs a me 12 mau papa i hoʻomākaukau ʻia e kūkulu ʻia e nā hui like ʻole a me nā kaiāulu ma lalo o nā laikini manuahi (BSD, MIT, Apache 12).
Source: opennet.ru