Qhov project Vortex 3.0, uas tsim ib qho GPGPU qhib-qhov chaw raws li RISC-V cov qauv teeb tsa kev qhia thiab yog tsim los rau kev suav sib luag siv OpenCL API thiab SIMT (Single Instruction, Multiple Threads) tus qauv ua haujlwm, tam sim no muaj. Qhov project no kuj tseem siv tau rau kev tshawb fawb 3D graphics thiab kev tsim cov GPU architectures tshiab. Cov schematics, cov lus piav qhia txog cov khoom siv hauv Verilog, simulator, drivers, thiab cov ntaub ntawv tsim qauv nrog rau tau muab faib rau hauv qab daim ntawv tso cai Apache 2.0.
GPGPU yog raws li tus qauv RISC-V ISA, txuas ntxiv nrog cov lus qhia ntxiv los txhawb GPU cov yam ntxwv thiab kev tswj hwm xov. Kev hloov pauv rau RISC-V cov lus qhia teeb tsa architecture raug khaws cia kom tsawg kawg nkaus, thiab cov lus qhia vector uas twb muaj lawm raug siv thaum twg ua tau. Cov lus qhia ntxiv suav nrog: "tex" rau kev ua kom nrawm dua cov qauv; vx_rast rau kev tswj hwm rasterization; vx_rop rau kev ua cov ntu, qhov tob, thiab pob tshab; vx_imadd rau kev ua haujlwm ntau thiab ntxiv; vx_wspawn, vx_split, vx_join, vx_tmc, thiab vx_bar rau kev ua kom cov pab pawg ntawm cov xov (wavefronts) ua haujlwm sib luag los ntawm SIMD Engine.
Lub GPGPU uas tab tom tsim txhawb nqa 32- thiab 64-ntsis RISC-V RV32IMF thiab RV64IMAFD cov qauv qhia teeb tsa thiab tuaj yeem suav nrog kev xaiv sib koom nco, L1, L2, thiab L3 caches, thiab tus lej teeb tsa tau ntawm cov cores, warps, thiab threads. Txhua lub core kuj tseem tuaj yeem suav nrog tus lej teeb tsa tau ntawm ALUs, FPUs, LSUs, thiab SFUs. Xilinx thiab Altera FPGAs tuaj yeem siv rau prototyping, thiab Verilator (Verilog simulator), RTLSIM (RTL simulation), thiab SimX (software simulation) tuaj yeem siv rau kev sim chip.
Rau kev tsim daim ntawv thov, muaj cov cuab yeej siv, suav nrog Vortex-adapted versions ntawm PoCL (OpenCL compiler thiab runtime), LLVM/Clang, GCC, thiab Binutils. Qhov project txhawb nqa OpenCL 1.2 specification thiab siv kev txhawb nqa rau SPIR-V intermediate sawv cev ntawm shaders los ntawm kev txhais lus rau OpenCL.
Cov kev hloov pauv hauv Vortex 3.0 suav nrog:
- Ib qho khoom siv kho vajtse graphics stack tau ntxiv lawm, suav nrog cov blocks rau rasterization, texture mapping, thiab output merging (OM). Ib qho Vulkan driver, vortexpipe, tau tsim rau Mesa raws li cov graphics stack uas tau siv thiab lavapipe software rasterizer.
- Lub peev xwm ntawm Tensor Core, tsim los ua kom nrawm dua qhov kev ua tiav ntawm cov qauv kev kawm tshuab, tau nthuav dav, siv kev txhawb nqa rau kev sib txawv ntawm cov qauv rau kev nias cov matrices hnyav.
- Qhov kev ua haujlwm WGMMA (warpgroup-level matrix multiplication) tau siv rau kev sib npaug ntawm matrix hauv hom asynchronous.
- Ntxiv DXA (Kev Hloov Cov Ntaub Ntawv Sai) lub cav kom ua kom cov ntaub ntawv hloov pauv sai dua los ntawm lub cim xeeb thoob ntiaj teb mus rau lub cim xeeb hauv zos.
- Ib lub architecture tshiab tau raug siv raws li lub processor hais kom ua (CP) thiab lub hardware scheduler ntawm computing cores (KMU - Kernel Management Unit), uas tso cai rau kev xa cov xov computing mus rau sab chip.
- Muaj ib lub tsev qiv ntawv tshiab uas siv tau rau lub sijhawm ua haujlwm uas ua haujlwm hauv hom tsis thaiv thiab muab cov lus piav qhia uas txhais ua cov lus txib kho vajtse uas ua haujlwm tsis sib xws. Cov kab, cov xwm txheej, cov modules, thiab kev sib dhos raws li cov teeb meem tsis sib xws nrog cov lus piav qhia txog kev tuaj txog/tos/kev tshwm sim raug txhawb nqa.
- Ntxiv kev txhawb nqa rau RISC-V Shortened Instructions (RVC).
- Kev txhawb nqa kho vajtse rau kev ua haujlwm atomic (Hardware Atomics) tau raug siv.
- Lub FPU tau raug tsim dua tshiab tag nrho thiab cov khoom sib ntxiv tshiab (Wallace-tree, Folded-radix) thiab adder (Kogge-Stone) tau raug qhia tawm.
- Ntxiv ib lub virtual memory stack raws li lub memory management unit (MMU) nrog kev txhawb nqa rau 32-bit SV32 virtual addressing architecture.
- Kev txhawb nqa rau RISC-V Zicond txuas ntxiv nrog kev siv cov haujlwm ua haujlwm.
- Lub moos sib xyaw ua ke.
- Kev txhawb nqa rau HIP (Heterogeneous Interface for Portability) lus tau raug siv los ntawm chipStar framework, uas txhais HIP mus rau hauv SPIR-V.
- Kev koom ua ke tag nrho nrog GEM5 simulator tau muab, thiab kev txhawb nqa rau SimX simulator ntawm TLM (Transaction-Level Modeling) architecture tau ntxiv.
- Ntxiv kev txhawb nqa rau Synopsys thiab Yosys toolkits rau kev sib xyaw ua ke rau kev tsim cov chip, nrog rau kev txhawb nqa rau kev siv ASAP7 (7nm), SAED14 (14nm), thiab NanGate (15nm) cov tsev qiv ntawv txheem.
- Cov cuab yeej siv tau hloov kho rau LLVM 20 thiab POCL 7.0.
Tau qhov twg los: opennet.ru
