Lub kaw lus tsim tau raug hloov mus siv Python 3. Yog tias Python 3 tsis muaj, nws tuaj yeem rov qab mus siv Python 2.
Lub hauv ntej kawg nrog lub compiler rau Go lus (llgo) tsis suav nrog kev tso tawm, uas tej zaum yuav raug kho dua tshiab yav tom ntej.
Lub vector-function-abi-variant tus cwj pwm tau muab ntxiv rau qhov nruab nrab sawv cev (IR) los piav qhia txog kev ua haujlwm ntawm scalar thiab vector functions rau vectorize hu. Los ntawm llvm::VectorType muaj ob hom vector hom llvm::FixedVectorType thiab llvm::ScalableVectorType.
Branching raws li udef qhov tseem ceeb thiab dhau undef qhov tseem ceeb rau cov qauv tsev qiv ntawv ua haujlwm tau lees paub tias yog tus cwj pwm tsis tau hais tseg. IN
memset/memcpy/memmove tso cai hla undef pointers, tab sis yog hais tias tus parameter nrog loj yog xoom.
LLJIT tau ntxiv kev txhawb nqa rau kev ua haujlwm zoo li qub los ntawm LLJIT::initialize thiab LLJIT::deinitialize txoj kev. Muaj peev xwm ntxiv cov tsev qiv ntawv zoo li qub rau JITDylib siv cov chav kawm StaticLibraryDefinitionGenerator tau ua tiav. Ntxiv C API rau ORCv2 (API rau tsim JIT compilers).
Kev them nyiaj yug rau Cortex-A64, Cortex-A34, Cortex-A77 thiab Cortex-X78 processors tau ntxiv rau qhov backend rau AArch1 architecture. Ua tiav ARMv8.2-BF16 (BFloat16) thiab ARMv8.6-A txuas ntxiv, suav nrog RMv8.6-ECV (Enhanced Counter Virtualization), ARMv8.6-FGT (Fine Grained Traps), ARMv8.6-AMU (Kev Ua Haujlwm Saib Xyuas virtualization) thiab ARMv8.0-DGH (Cov ntaub ntawv sib sau ua ke). Lub peev xwm los tsim cov cai rau kev ua haujlwm-txhim kho rau SVE vector cov lus qhia tau muab.
Kev them nyiaj yug rau Cortex-M55, Cortex-A77, Cortex-A78 thiab Cortex-X1 processors tau ntxiv rau qhov backend rau ARM architecture. Extensions tau siv
Armv8.6-A Matrix Multiply thiab RMv8.2-AA32BF16 BFloat16.
Kev them nyiaj yug rau code tiam rau POWER10 processors tau ntxiv rau lub backend rau PowerPC architecture. Loop optimizations tau nthuav dav thiab kev txhawb nqa ntab taw tes tau txhim kho.
Lub backend rau RISC-V architecture tso cai rau kev lees paub ntawm thaj ua rau thaj uas txhawb nqa cov kev qhia txuas ntxiv uas tseem tsis tau pom zoo.
Lub backend rau AVR architecture tau raug xa mus los ntawm kev sim qeb kom ruaj khov, suav nrog hauv kev faib tawm yooj yim.
Lub backend rau x86 architecture txhawb Intel AMX thiab TSXLDTRK cov lus qhia. Ntxiv kev tiv thaiv tawm tsam LVI (Load Value Injection), thiab tseem siv cov kev ua haujlwm dav dav ntawm Kev Ua Phem Txhaum Cai los thaiv kev tawm tsam los ntawm kev xav txog kev ua haujlwm ntawm CPU.