{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/hr\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"Projekt VeriGPU razvija otvoreni GPU na jeziku Verilog","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Projekt VeriGPU usmjeren je na stvaranje otvorenog GPU-a, razvijenog na jeziku za opis i modeliranje elektroni\u010dkih sustava Verilog. U po\u010detku se projekt razvija koriste\u0107i Verilog simulator, ali nakon \u0161to postane spreman, mo\u0107i \u0107e se koristiti za proizvodnju stvarnih \u010dipova. Rezultati projekta distribuiraju se pod MIT licencom. <\/p>\n

VeriGPU se pozicionira kao specijalizirani procesor (ASIC), optimiziran za ubrzanje izra\u010duna povezanih sa sustavima strojnog u\u010denja. U planu se spominje osiguranje kompatibilnosti s frameworkom dubokog strojnog u\u010denja PyTorch i implementacija mogu\u0107nosti razvoja aplikacija za VeriGPU koriste\u0107i HIP API (Heterogeneous-Compute Interface). U budu\u0107nosti se ne isklju\u010duje dodavanje podr\u0161ke za druge API-e, kao \u0161to su SYCL i NVIDIA CUDA. <\/p>\n

GPU se razvija na osnovi RISC-V skupa naredbi, ali kona\u010dna unutra\u0161nja arhitektura skupa naredbi GPU-a slabo je kompatibilna s RISC-V ISA, budu\u0107i da u situacijama kada projektiranje GPU-a ne odgovara RISC-V prikazu, cilj nije o\u010duvanje kompatibilnosti s RISC-V. Razvoj je fokusiran na mogu\u0107nosti potrebne za sustave strojnog u\u010denja, stoga se radi smanjenja veli\u010dine i slo\u017eenosti matrice \u010dipa koristi samo format izra\u010duna s pomi\u010dnom to\u010dkom BF16, a dostupne su samo tra\u017eene operacije s pomi\u010dnom to\u010dkom za strojno u\u010denje, kao \u0161to su exp, log, tanh i sqrt. <\/p>\n

Dostupni komponenti uklju\u010duju GPU kontroler, APU (Accelerated Processing Unit) za cijelobrojne operacije (+, -, \/, *), blok za operacije s pomi\u010dnom to\u010dkom (+, *) i blok za upravljanje grananjem. Za razvoj aplikacija ponu\u0111eni su assembler i podr\u0161ka za kompilaciju koda u C++ temeljenog na LLVM. Me\u0111u planiranim mogu\u0107nostima isti\u010du se paralelno izvr\u0161avanje instrukcija, ke\u0161iranje podataka u memoriji i instrukcija, te SIMT (Single instruction multiple thread) operacije.

\"Projekt<\/center>
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Izvor: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103861,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103860","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Projekt VeriGPU razvija otvoreni GPU na jeziku Verilog | ProHoster","description":"Projekt VeriGPU usmjeren je na stvaranje otvorenog GPU-a, razvijenog na jeziku za opis i modeliranje elektroni\u010dkih sustava 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