{"id":77492,"date":"2020-04-10T19:42:45","date_gmt":"2020-04-10T17:42:45","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe"},"modified":"2020-04-10T19:42:45","modified_gmt":"2020-04-10T17:42:45","slug":"poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe","status":"publish","type":"post","link":"https:\/\/prohoster.info\/hr\/blog\/news\/poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe","title":{"rendered":"Pazi, ARM? Novi 64-bitni jezgreni Synopsys ARC pove\u0107at \u0107e performanse tri puta","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Malo tko zna da je procesorska arhitektura ARC jedna od najra\u0161irenijih arhitektura uz ARM, MIPS i x86. Razvijena 1980-ih godina, arhitektura ARC koristi se u raznim mikro kontrolerima za \u0161irok spektar visoko tehnolo\u0161kih proizvoda, a svake godine na osnovi ARC proizvodi se oko 1,5 milijardi<\/a><\/noindex> ure\u0111aja.<\/p>\n

Nedavno je korporacija Synopsys najavila novu generaciju 32- i 64-bitnih procesorskih jezgri ARC, koje obe\u0107avaju trostruko pove\u0107anje performansi u odnosu na prethodnike, te omogu\u0107uju izgradnju sustava na \u010dipu s 12 jezgri. Tako \u0107e nove jezgre omogu\u0107iti Synopsysu natjecanje s ARM-om na nizu novih podru\u010dja.<\/p>\n

«Ugra\u0111ene aplikacije poput kontrolera za \u010dvrste diskove ili mre\u017enu opremu postaju sve slo\u017eenije, \u0161to zahtijeva zna\u010dajno pove\u0107anje performansi pri ograni\u010denoj potro\u0161nji energije i veli\u010dini», rekao je John Koeter, vi\u0161i potpredsjednik za marketing i strategiju intelektualnog vlasni\u0161tva u Synopsysu. «S lansiranjem nove arhitekture ARCv3 i jezgri ARC HS5x i HS6x, programeri \u0107e biti u mogu\u0107nosti zadovoljiti rastu\u0107e zahtjeve za performansama svojih SoC-a danas i u budu\u0107nosti».<\/p>\n

\"Pazi,
\n<\/center><\/p>\n

Nove obitelji procesora Synopsys DesignWare ARC uklju\u010duju 32-bitne jezgre HS56\/HS57D\/HS58<\/a><\/noindex> i 64-bitne jezgre HS66\/HS68<\/a><\/noindex>. Svje\u017ee najavljeni procesori namijenjeni su \u0161irokom spektru aplikacija, poput kontrolera za \u010dvrste diskove (SSD), mre\u017enih kontrolera, autopilota za vozila, infotainment sustava za automobile i mnogih drugih. Uzimaju\u0107i u obzir rastu\u0107e zahtjeve za kapacitetom radne memorije, 64-bitni ARC HD6x omogu\u010diti \u0107e izradu sustava s 4,5 PB DRAM-a, dok \u0107e ure\u0111aji na bazi ARC HD5x morati ostati s manjim kapacitetima. Ipak, stvarni kapaciteti podr\u017eane radne memorije vjerojatno \u0107e biti odre\u0111eni operacijskim sustavom, a vidljive prednosti 64-bitnih CPU-a - \u0161irem cjevovodu i ve\u0107em broju registara.<\/p>\n

\u0160to se ti\u010de arhitektura DesignWare ARC HS5x i DesignWare ARC HS6x, one podr\u017eavaju skup instrukcija ARCv3, koji se mo\u017ee pro\u0161iriti APEX instrukcijama (ARC Processor EXtensions), ako klijentima zatreba ne\u0161to specifi\u010dno. Osim toga, ARC HS57D je opremljen digitalnim signalnim procesorom ARCv3DSP koji podr\u017eava 150 instrukcija. Nova jezgra imaju dubinu cevi od 10 nivoa, mogu izvr\u0161avati dvije instrukcije po taktu, a opremljena su 128-bitnim modulom za operacije s pomi\u010dnom zarezom. Pri tome, najnaprednije verzije jezgri podr\u017eavaju drugu razinu ke\u0161a (L2) veli\u010dine do 16 MB.<\/p>\n

\"Pazi,<\/p>\n

Kada je rije\u010d o performansama, Synopsys navodi 3 DMIPS po MHz u cjelobrojnim prora\u010dunima, kao i 5,1 CoreMark po MHz, \u0161to je vrlo dobro za mini jezgre s minimalnom potro\u0161njom energije. Tako, 3 DMIPS po MHz — to je vi\u0161e od prili\u010dno sna\u017enih procesora Cortex-A55<\/a><\/noindex>, dok je 5,1 CoreMark po MHz — vi\u0161e od bilo kojeg ARM procesora za mikroprocesore.<\/a><\/noindex><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Procesorska jezgra Synopsys DesignWare ARC HS5x i HS6x
<\/strong><\/p>\n<\/td>\n<\/tr>\n

<\/td>\nHS5x<\/td>\nHS6x<\/td>\n<\/tr>\n
<\/td>\nHS56<\/td>\nHS57D<\/td>\nHS58<\/td>\nHS66<\/td>\nHS68<\/td>\n<\/tr>\n
Skup instrukcija<\/td>\nARCv3<\/td>\n<\/tr>\n
APEX instrukcije<\/td>\nPodr\u017eani<\/td>\n<\/tr>\n
Bitna \u0161irina<\/td>\n32-bita<\/td>\n64-bita<\/td>\n<\/tr>\n
Instrukcija po taktu<\/td>\n2<\/td>\n<\/tr>\n
Duljina cevovoda<\/td>\n10 nivoa<\/td>\n<\/tr>\n
DSP<\/td>\n\u2014<\/td>\nARCv3DSP
150 instrukcija<\/td>\n		\u2014<\/td>\n\u2014<\/td>\n\u2014<\/td>\n<\/tr>\n
Ta\u010dnost FPU<\/td>\nFP16, FP32, FP64<\/td>\n<\/tr>\n
Procesorski klaster<\/td>\n12 jezgri<\/td>\n<\/tr>\n
Ubrziva\u010da po klasteru<\/td>\n16 ubrziva\u010da<\/td>\n<\/tr>\n
L1<\/td>\nKe\u0161 instrukcija + Ke\u0161 podataka<\/td>\n<\/tr>\n
L2<\/td>\n\u2014<\/td>\n\u2014<\/td>\n16 MB<\/td>\n\u2014<\/td>\n16 MB<\/td>\n<\/tr>\n
Maksimalni kapacitet memorije<\/td>\n64 GB (ovisno o OS-u)<\/td>\n4,5 Petabajta<\/td>\n<\/tr>\n
Frekvencija (na t\/p 16FFC)<\/td>\n1,8 GHz<\/td>\n<\/tr>\n
DMIPS<\/td>\n5400 DMIPS po jezgri \/ 3 DMIPS po MHz<\/td>\n<\/tr>\n
CoreMark<\/td>\n9180 CoreMark po jezgri \/ 5,1 CoreMark po MHz<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Jedna od klju\u010dnih osobina nove porodice DesignWare ARC HS5x i DesignWare ARC HS6x je mogu\u0107nost stvaranja sustava na \u010dipu (system-on-chip, SoC) s 12 op\u0107im procesorskim jezgrama i 16 specijaliziranih ubrziva\u010da. Svaka jezgra\/ubrziva\u010d u takvom procesoru radi na vlastitoj takt frekvenciji i koristi vlastiti sustav napajanja kako bi maksimizirao energetsku u\u010dinkovitost. Zajedno s novim jezgrama, Synopsys tako\u0111er nudi i intra-procesorsku ke\u0161 koherentnu povezanost s brzinom prijenosa podataka od 800 GB\/s. <\/p>\n

SoC temeljen na ARC arhitekturi danas nije ba\u0161 rasprostranjen, ali s obzirom na perspektivne procesore za sustave autonomnog upravljanja, pohranu podataka, upravljanje protokom podataka, vi\u0161ekorisni\u010dku obradu i razne akceleratore, bit \u0107e vrlo korisni. Ovo \u0107e omogu\u0107iti tvrtki Synopsys da se natje\u010de s ARM jezgrama za mjesto u SoC-ima za navedene aplikacije, \u0161to do sada nije bilo slu\u010daj. Tako su jezgre DesignWare ARC HS5x i DesignWare ARC HS6x ve\u0107 izazvale interes proizvo\u0111a\u010da \u010dvrstih diskova Starblaze. <\/p>\n

«Razvijatelji visokih performansi ugra\u0111enih rje\u0161enja konstantno se suo\u010davaju s novim izazovima u postizanju visokih performansi uz velike kapacitete memorije i ograni\u010denja u pogledu potro\u0161nje energije i veli\u010dina», rekao je Bruce Cheng, glavni znanstveni savjetnik Starblaze. «Mogu\u0107nosti novih 32-bitnih procesora ARC HS5x i 64-bitnih procesora HS6x tvrtke Synopsys u podru\u010dju vi\u0161ejezgrenosti omogu\u0107iti \u0107e nam prelazak na novu razinu u\u010dinkovitosti potro\u0161nje energije, koja nije ponu\u0111ena drugim procesorima koji su trenutno dostupni na tr\u017ei\u0161tu».<\/p>\n

\"Pazi,<\/p>\n

Synopsys \u0107e po\u010deti nuditi jezgre ARC HS56, HS57D, HS58, HS66, HS68, kao i njihove multiprocesorske verzije HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP, po\u010dev\u0161i od tre\u0107eg kvartala 2020. godine. Tako\u0111er, tvrtka \u0107e ponuditi paket ARC MetaWare Development Toolkit za izradu \u010dipova temeljenih na ovim jezgrama, kao i simulator i verifikator za provjeru funkcionalnosti SoC-a prije realizacije na siliciju. \u0160to se ti\u010de podr\u0161ke sa strane operativnih sustava, nove jezgre bit \u0107e kompatibilne s nizom Linux distribucija, Zephyr, kao i raznim proprietarnim operativnim sustavima.<\/p>\n

<\/p>\n

<\/center><\/p>\n

\t\t\t\t


\n\t\t\t\t\t\t\t\t<\/center>
Izvor: 3dnews.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041d\u0435\u043c\u043d\u043e\u0433\u0438\u0435 \u0437\u043d\u0430\u044e\u0442, \u0447\u0442\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043d\u0430\u044f \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 ARC \u044f\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u043e\u0434\u043d\u043e\u0439 \u0438\u0437 \u0441\u0430\u043c\u044b\u0445 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u0435\u043d\u043d\u044b\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440 \u043d\u0430\u0440\u044f\u0434\u0443 \u0441 ARM, MIPS \u0438 x86. \u0420\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d\u043d\u0430\u044f \u0432 1980-\u0445 \u0433\u043e\u0434\u0430\u0445, \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 ARC \u043f\u0440\u0438\u043c\u0435\u043d\u044f\u0435\u0442\u0441\u044f \u0432 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0445 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430\u0445 \u0434\u043b\u044f \u0448\u0438\u0440\u043e\u0447\u0430\u0439\u0448\u0435\u0433\u043e \u0441\u043f\u0435\u043a\u0442\u0440\u0430 \u0432\u044b\u0441\u043e\u043a\u043e\u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0447\u043d\u043e\u0439 \u043f\u0440\u043e\u0434\u0443\u043a\u0446\u0438\u0438, \u0430 \u043a\u0430\u0436\u0434\u044b\u0439 \u0433\u043e\u0434 \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 ARC \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0441\u044f \u043e\u043a\u043e\u043b\u043e 1,5 \u043c\u0438\u043b\u043b\u0438\u0430\u0440\u0434\u0430 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432. \u041d\u0430 \u0434\u043d\u044f\u0445 \u043a\u043e\u0440\u043f\u043e\u0440\u0430\u0446\u0438\u044f Synopsys \u0430\u043d\u043e\u043d\u0441\u0438\u0440\u043e\u0432\u0430\u043b\u0430 \u043d\u043e\u0432\u043e\u0435 \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u0435 32- \u0438 64-\u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043d\u044b\u0445 […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":77493,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-77492","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Pazi se, ARM? Novi 64-bitni jezgre Synopsys ARC pove\u0107at \u0107e performanse tri puta | ProHoster","description":"Malo tko zna da je ARC arhitektura procesora jedna od najrasprostranjenijih arhitektura uz ARM, MIPS i x86.","canonical_url":"https:\/\/prohoster.info\/hr\/blog\/news\/poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe","robots":"max-image-preview:large","keywords":"","webmasterTools":{"miscellaneous":""},"schema":null,"og:locale":"hr_HR","og:site_name":"ProHoster | \u041a\u0443\u043f\u0438\u0442\u044c \u043d\u0430\u0434\u0435\u0436\u043d\u044b\u0439 \u0445\u043e\u0441\u0442\u0438\u043d\u0433 \u0434\u043b\u044f \u0441\u0430\u0439\u0442\u043e\u0432 \u0441 \u0437\u0430\u0449\u0438\u0442\u043e\u0439 \u043e\u0442 DDoS, VPS VDS \u0441\u0435\u0440\u0432\u0435\u0440\u044b","og:type":"article","og:title":"\ud83e\udd47\u041f\u043e\u0431\u0435\u0440\u0435\u0433\u0438\u0441\u044c, ARM? \u041d\u043e\u0432\u044b\u0435 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