{"id":84726,"date":"2020-06-10T13:42:19","date_gmt":"2020-06-10T11:42:19","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v"},"modified":"2020-06-10T13:42:19","modified_gmt":"2020-06-10T11:42:19","slug":"mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/hu\/blog\/news\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","title":{"rendered":"A seL4 mikrokernel matematikailag verifik\u00e1lt RISC-V architekt\u00far\u00e1hoz","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

RISC-V Alap\u00edtv\u00e1ny bejelentette<\/a><\/noindex> a mikrokernel m\u0171k\u00f6d\u00e9s\u00e9nek verifik\u00e1ci\u00f3j\u00e1r\u00f3l seL4<\/a><\/noindex> RISC-V utas\u00edt\u00e1sk\u00e9szlet architektur\u00e1j\u00fa rendszereken. A verifik\u00e1ci\u00f3 l\u00e9nyege matematikai bizony\u00edt\u00e1sa<\/a><\/noindex> a seL4 megb\u00edzhat\u00f3s\u00e1g\u00e1nak, amely tan\u00fas\u00edtja a form\u00e1lis nyelven megfogalmazott specifik\u00e1ci\u00f3knak val\u00f3 teljes megfelel\u00e9st. A megb\u00edzhat\u00f3s\u00e1g bizony\u00edt\u00e1sa lehet\u0151v\u00e9 teszi<\/a><\/noindex> a seL4 haszn\u00e1lat\u00e1t kritikus fontoss\u00e1g\u00fa RISC-V RV64 processzorokra \u00e9p\u00fcl\u0151 rendszerekben, amelyeket megn\u00f6velt megb\u00edzhat\u00f3s\u00e1gi szint ig\u00e9nyel, \u00e9s garant\u00e1lja a meghib\u00e1sod\u00e1sok hi\u00e1ny\u00e1t. A seL4 kernelen m\u0171k\u00f6d\u0151 szoftverfejleszt\u0151k teljesen biztosak lehetnek abban, hogy ha a rendszer egyik r\u00e9sz\u00e9ben hiba l\u00e9p fel, ez a hiba nem terjed \u00e1t a rendszer t\u00f6bbi r\u00e9sz\u00e9re, k\u00fcl\u00f6n\u00f6sen a kritikus r\u00e9szekre. <\/p>\n

Eredetileg a seL4 mikrokernel 32-bites ARM folyamatorkezel\u0151kh\u00f6z volt verifik\u00e1lva, k\u00e9s\u0151bb pedig 64-bites x86 folyamatorkezel\u0151kh\u00f6z. Megjegyzend\u0151, hogy a RISC-V ny\u00edlt hardverarchitekt\u00fara \u00e9s a ny\u00edlt seL4 mikrokernel kombin\u00e1ci\u00f3ja \u00faj szint\u0171 biztons\u00e1got eredm\u00e9nyez, mivel a hardverkomponensek a j\u00f6v\u0151ben teljes m\u00e9rt\u00e9kben verifik\u00e1lhat\u00f3k lesznek, ami nem lehets\u00e9ges a z\u00e1rt hardverarchitekt\u00far\u00e1k eset\u00e9ben. <\/p>\n

A seL4 valid\u00e1l\u00e1sakor az a felt\u00e9telez\u00e9s, hogy a hardver a megadottak szerint m\u0171k\u00f6dik, \u00e9s a specifik\u00e1ci\u00f3 teljes m\u00e9rt\u00e9kben le\u00edrja a rendszer viselked\u00e9s\u00e9t, de val\u00f3j\u00e1ban a hardver nem mentes a hib\u00e1kt\u00f3l, amit j\u00f3l mutatnak a rendszeres kih\u00edv\u00e1sok a spekulat\u00edv utas\u00edt\u00e1s-v\u00e9grehajt\u00e1si mechanizmusban. Az ny\u00edlt hardverplatformok megk\u00f6nny\u00edtik a biztons\u00e1ggal kapcsolatos m\u00f3dos\u00edt\u00e1sok integr\u00e1l\u00e1s\u00e1t \u2014 p\u00e9ld\u00e1ul az \u00f6sszes lehets\u00e9ges adat\u00e1tviteli csatorna blokkol\u00e1s\u00e1ra, ahol sokkal hat\u00e9konyabb a hardveres megold\u00e1s, mint a szoftveres ker\u00fcl\u0151utak keres\u00e9se.<\/p>\n

Eml\u00e9keztet\u0151\u00fcl, a seL4 architekt\u00fara figyelemre m\u00e9lt\u00f3<\/a><\/noindex> A kernel microkernel abstracts management parts into user space and employs similar access control mechanisms for these resources as for user resources. The microkernel does not provide ready-made high-level abstractions for managing files, processes, network connections, etc.; instead, it offers only minimal mechanisms for accessing physical address space, handling interrupts, and CPU resources. High-level abstractions and drivers for interacting with hardware are implemented separately on top of the microkernel as tasks executed at the user level. Access to the resources available to the microkernel by these tasks is organized through the definition of rules.<\/p>\n

A RISC-V ny\u00edlt \u00e9s rugalmas g\u00e9pi utas\u00edt\u00e1sok rendszere, amely lehet\u0151v\u00e9 teszi k\u00fcl\u00f6nf\u00e9le alkalmaz\u00e1s\u00fa mikroprocesszorok l\u00e9trehoz\u00e1s\u00e1t, mik\u00f6zben nem ig\u00e9nyel d\u00edjakat \u00e9s nem t\u00e1maszt haszn\u00e1lati felt\u00e9teleket. A RISC-V lehet\u0151v\u00e9 teszi teljesen ny\u00edlt SoC-k \u00e9s processzorok l\u00e9trehoz\u00e1s\u00e1t. Jelenleg a RISC-V specifik\u00e1ci\u00f3n alapul\u00f3 k\u00fcl\u00f6nb\u00f6z\u0151 c\u00e9gek \u00e9s k\u00f6z\u00f6ss\u00e9gek \u00e1ltal k\u00fcl\u00f6nb\u00f6z\u0151 ny\u00edlt licencjogok (BSD, MIT, Apache 2.0) alatt t\u00f6bb tucatnyi mikroprocesszor-architekt\u00far\u00e1t, SoC-t \u00e9s m\u00e1r el\u0151\u00e1ll\u00edtott chipet t\u00e1mogatnak. Go nyelven fejl\u0151dik.<\/a><\/noindex> A RISC-V t\u00e1mogat\u00e1sa a Glibc 2.27, a binutils 2.30, a gcc 7 \u00e9s a Linux 4.15 verzi\u00f3k megjelen\u00e9s\u00e9vel kezd\u0151d\u00f6tt.<\/p>\n

<\/a><\/noindex><\/p>\n

Forr\u00e1s: opennet.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041e\u0440\u0433\u0430\u043d\u0438\u0437\u0430\u0446\u0438\u044f RISC-V Foundation \u0441\u043e\u043e\u0431\u0449\u0438\u043b\u0430 \u043e \u0432\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u0438 \u0440\u0430\u0431\u043e\u0442\u044b \u043c\u0438\u043a\u0440\u043e\u044f\u0434\u0440\u0430 seL4 \u043d\u0430 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u0445 \u0441 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043e\u0439 \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V. \u0412\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f \u0441\u0432\u043e\u0434\u0438\u0442\u0441\u044f \u043a \u043c\u0430\u0442\u0435\u043c\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u043e\u043c\u0443 \u0434\u043e\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u0443 \u043d\u0430\u0434\u0451\u0436\u043d\u043e\u0441\u0442\u0438 \u0440\u0430\u0431\u043e\u0442\u044b seL4, \u043a\u043e\u0442\u043e\u0440\u043e\u0435 \u0441\u0432\u0438\u0434\u0435\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u0443\u0435\u0442 \u043e \u043f\u043e\u043b\u043d\u043e\u043c \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0438\u0438 \u0437\u0430\u0434\u0430\u043d\u043d\u044b\u043c \u043d\u0430 \u0444\u043e\u0440\u043c\u0430\u043b\u044c\u043d\u043e\u043c \u044f\u0437\u044b\u043a\u0435 \u0441\u043f\u0435\u0446\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f\u043c. \u0414\u043e\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u043e \u043d\u0430\u0434\u0451\u0436\u043d\u043e\u0441\u0442\u0438 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c seL4 \u0432 \u043a\u0440\u0438\u0442\u0438\u0447\u0435\u0441\u043a\u0438 \u0432\u0430\u0436\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u0445 \u043d\u0430 \u0431\u0430\u0437\u0435 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 RISC-V RV64, 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