ื”ื‘ืœืชื™ ื ืžื ืข ืฉืœ ื—ื“ื™ืจืช FPGA ืœืžืจื›ื–ื™ ื ืชื•ื ื™ื

ื”ื‘ืœืชื™ ื ืžื ืข ืฉืœ ื—ื“ื™ืจืช FPGA ืœืžืจื›ื–ื™ ื ืชื•ื ื™ื
ืืชื” ืœื ืฆืจื™ืš ืœื”ื™ื•ืช ืžืขืฆื‘ ืฉื‘ื‘ื™ื ื›ื“ื™ ืœืชื›ื ืช ืขื‘ื•ืจ FPGAs, ื‘ื“ื™ื•ืง ื›ืžื• ืฉืืชื” ืœื ืฆืจื™ืš ืœื”ื™ื•ืช ืžืชื›ื ืช C++ ื›ื“ื™ ืœื›ืชื•ื‘ ืงื•ื“ ื‘-Java. ืขื ื–ืืช, ื‘ืฉื ื™ ื”ืžืงืจื™ื ื–ื” ื›ื ืจืื” ื™ื”ื™ื” ืฉื™ืžื•ืฉื™.

ื”ืžื˜ืจื” ืฉืœ ืžืกื—ื•ืจ ื”ืŸ ื˜ื›ื ื•ืœื•ื’ื™ื•ืช Java ื•ื”ืŸ FPGA ื”ื™ื ืœื”ืคืจื™ืš ืืช ื”ื˜ืขื ื” ื”ืื—ืจื•ื ื”. ื—ื“ืฉื•ืช ื˜ื•ื‘ื•ืช ืขื‘ื•ืจ FPGAs - ืฉื™ืžื•ืฉ ื‘ืฉื›ื‘ื•ืช ื”ื”ืคืฉื˜ื” ื•ื‘ืขืจื›ืช ื”ื›ืœื™ื ื”ื ื›ื•ื ื™ื, ื‘-35 ื”ืฉื ื™ื ื”ืื—ืจื•ื ื•ืช ืžืื– ื”ืžืฆืืช ื”ืชืงืŸ ื”ืœื•ื’ื™ืงื” ื”ื ื™ืชืŸ ืœืชื›ื ื•ืช, ื™ืฆื™ืจืช ืืœื’ื•ืจื™ืชืžื™ื ื•ื–ืจื™ืžื•ืช ื ืชื•ื ื™ื ืขื‘ื•ืจ FPGAs ื‘ืžืงื•ื CPUs, DSPs, GPUs ืื• ื›ืœ ืฆื•ืจื” ืื—ืจืช ืฉืœ ASIC ืžื•ืชืืžื™ื ืื™ืฉื™ืช ื”ืคื›ื” ื™ื•ืชืจ ื•ื™ื•ืชืจ ื ืคื•ืฅ. ืงืœ ื™ื•ืชืจ.

ื”ืขื“ื›ื ื™ื•ืช ื”ืžื“ื”ื™ืžื” ืฉืœ ื™ืฆื™ืจืชื ื ื™ื›ืจืช ื‘ืขื•ื‘ื“ื” ืฉื‘ื“ื™ื•ืง ื›ืืฉืจ ืžืขื‘ื“ื™ ื”ืžืขื‘ื“ื™ื ื›ื‘ืจ ืœื ื™ื›ืœื• ืœื”ื™ืฉืืจ ืžื•ื“ื•ืœ ื”ืžื—ืฉื•ื‘ ื”ื™ื—ื™ื“ ืฉืœ ืžืจื›ื–ื™ ื ืชื•ื ื™ื ืœื‘ื™ืฆื•ืข ืžืฉื™ืžื•ืช ืจื‘ื•ืช - ืžืžื’ื•ื•ืŸ ืกื™ื‘ื•ืช - ืจื›ื™ื‘ื™ FPGA ื”ืฉื™ื’ื• ืืช ื”ื™ืขื™ืœื•ืช ืฉืœื”ื, ื•ื”ืฆื™ืขื• ืžื”ื™ืจื•ืช, ื—ื‘ื™ื•ืŸ ื ืžื•ืš ื•ื™ื›ื•ืœื•ืช ืจืฉืช. ื•ื–ื™ื›ืจื•ืŸ - ื™ื›ื•ืœื•ืช ืžื—ืฉื•ื‘ ื”ื˜ืจื•ื’ื ื™ื•ืช ืฉืœ ืจื›ื™ื‘ื™ FPGA ืžื•ื“ืจื ื™ื™ื, ืฉื”ื ืžืขืจื›ื•ืช ืžื—ืฉื•ื‘ ื›ืžืขื˜ ืžืœืื•ืช. ืขื ื–ืืช, FPGAs ืžืฉื•ืœื‘ื™ื ื‘ื”ืฆืœื—ื” ื’ื ืขื ืžื›ืฉื™ืจื™ื ืื—ืจื™ื ื‘ืžืขืจื›ื•ืช ื”ื™ื‘ืจื™ื“ื™ื•ืช, ื•ืœื“ืขืชื ื•, ื”ื ืจืง ืžืชื—ื™ืœื™ื ืœืžืฆื•ื ืืช ืžืงื•ืžื ื”ืจืื•ื™ ื‘ื”ื™ืจืจื›ื™ื™ืช ื”ืžื—ืฉื•ื‘.

ื–ื• ื”ืกื™ื‘ื” ืฉืืจื’ื ื• ืืช ื›ื ืก ืคืœื˜ืคื•ืจืžืช FPGA Next ื‘ืกืŸ ื—ื•ื–ื” ื‘-22 ื‘ื™ื ื•ืืจ. ืžื˜ื‘ืข ื”ื“ื‘ืจื™ื, ืื—ื“ ืžืกืคืงื™ ื”-FPGA ื”ืขื™ืงืจื™ื™ื ื‘ืขื•ืœื ื•ื—ืœื•ืฆื” ื‘ืชื—ื•ื ื”ื•ื Xilinx. Ivo Bolsens, ืกื’ืŸ ื ืฉื™ื ื‘ื›ื™ืจ ื•ืงืฆื™ืŸ ื˜ื›ื ื•ืœื•ื’ื™ื” ืจืืฉื™ ื‘- Xilinx, ื ืื ื‘ื›ื ืก ื•ื ืชืŸ ืœื ื• ืืช ืžื—ืฉื‘ื•ืชื™ื• ื”ื™ื•ื ืขืœ ื”ืื•ืคืŸ ืฉื‘ื• Xilinx ืขื•ื–ืจืช ืœื™ืฆื•ืจ ืžืขืจื›ื•ืช ืžื—ืฉื•ื‘ ื”ื ื™ืชื ื•ืช ืœืฉื™ื ื•ื™ ืขื‘ื•ืจ ืžืจื›ื–ื™ ื ืชื•ื ื™ื.

ืœืงื— ืœืืจื›ื™ื˜ืงื˜ื™ื ื•ืžืชื›ื ืชื™ื ืฉืœ ืžืขืจื›ื•ืช ื”ืจื‘ื” ื–ืžืŸ ืœื”ืžืฆื™ื ืžืจื›ื– ื ืชื•ื ื™ื ื”ื˜ืจื•ื’ื ื™, ืฉื™ื›ืœื•ืœ ืกื•ื’ื™ื ืฉื•ื ื™ื ืฉืœ ื›ื•ื— ืžื—ืฉื‘ ืฉื™ืคืชื•ืจ ื‘ืขื™ื•ืช ื‘ืžื—ืฉื•ื‘, ืื—ืกื•ืŸ ื•ืจืฉืช. ื–ื” ื ืจืื” ื”ื›ืจื—ื™ ื‘ืฉืœ ื”ืขื•ื‘ื“ื” ืฉื ืขืฉื” ืงืฉื” ื™ื•ืชืจ ื•ื™ื•ืชืจ ืœื‘ืฆืข ืืช ื—ื•ืง ืžื•ืจ ื‘ืืžืฆืขื•ืช ื”ืชืงื ื™ CMOS ืฉื•ื ื™ื. ืœืขืช ืขืชื”, ื”ืฉืคื” ืฉืœื ื• ืขื“ื™ื™ืŸ ืžืชืžืงื“ืช ื‘ืžืขื‘ื“, ื•ืื ื—ื ื• ืขื“ื™ื™ืŸ ืžื“ื‘ืจื™ื ืขืœ "ื”ืืฆืช ื™ื™ืฉื•ืžื™ื", ื›ืœื•ืžืจ ืœื’ืจื•ื ืœืชื•ื›ื ื™ื•ืช ืœืคืขื•ืœ ื˜ื•ื‘ ื™ื•ืชืจ ืžืžื” ืฉื ื™ืชืŸ ืœืขืฉื•ืช ื‘ืžืขื‘ื“ื™ื ื‘ืœื‘ื“. ืขื ื”ื–ืžืŸ, ืžืจื›ื–ื™ ื ืชื•ื ื™ื ื™ื”ืคื›ื• ืœืื•ืกืคื™ื ืฉืœ ื›ื•ื— ืžื—ืฉื•ื‘, ืื—ืกื•ืŸ ื ืชื•ื ื™ื ื•ืคืจื•ื˜ื•ืงื•ืœื™ื ืฉืงื•ืฉืจื™ื ื”ื›ืœ ื™ื—ื“, ื•ื ื—ื–ื•ืจ ืœืžื•ื ื—ื™ื ื›ืžื• "ืžื—ืฉื•ื‘" ื•"ื™ื™ืฉื•ืžื™ื". ืžื—ืฉื•ื‘ ื”ื™ื‘ืจื™ื“ื™ ื™ื”ืคื•ืš ืœื ื•ืจืžืœื™ ื›ืžื• ืฉื™ืจื•ืชื™ ื”ืขื ืŸ ืฉืœ ื”ื™ื•ื ื”ืคื•ืขืœื™ื ืขืœ ืžื—ืฉื‘ื™ื ืฉื•ืœื—ื ื™ื™ื ืื• ื•ื™ืจื˜ื•ืืœื™ื™ื, ื•ื‘ืฉืœื‘ ืžืกื•ื™ื ืคืฉื•ื˜ ื ืฉืชืžืฉ ื‘ืžื™ืœื” "ืžื—ืฉื•ื‘" ื›ื“ื™ ืœืชืืจ ืื™ืš ื”ื ืขื•ื‘ื“ื™ื. ื‘ืฉืœื‘ ืžืกื•ื™ื - ื•ืกื‘ื™ืจ ืœื”ื ื™ื— ืฉ-FPGAs ื™ืกื™ื™ืขื• ืœืคืชื— ืขื™ื“ืŸ ื–ื” - ื ืงืจื ืœื–ื” ืฉื•ื‘ ืขื™ื‘ื•ื“ ื ืชื•ื ื™ื.

ืื™ืžื•ืฅ FPGAs ื‘ืžืจื›ื–ื™ ื ืชื•ื ื™ื ื™ื“ืจื•ืฉ ืฉื™ื ื•ื™ ื—ืฉื™ื‘ื”. "ื›ืฉื—ื•ืฉื‘ื™ื ืขืœ ื“ืจื›ื™ื ืœื”ืื™ืฅ ืืช ื”ื™ื™ืฉื•ืžื™ื ืฉืœ ื”ื™ื•ื, ืืชื” ืฆืจื™ืš ืœืจื“ืช ืœื™ืกื•ื“ื•ืช ืฉืœ ืื™ืš ื”ื ืคื•ืขืœื™ื, ื‘ืื™ืœื• ืžืฉืื‘ื™ื ืžืฉืชืžืฉื™ื, ืื™ืคื” ื”ื–ืžืŸ ืžื•ืฉืงืข", ืžืกื‘ื™ืจ ื‘ื•ืœื ืก. - ืืชื” ืฆืจื™ืš ืœืœืžื•ื“ ืืช ื”ื‘ืขื™ื” ื”ื›ืœืœื™ืช ืฉืืชื” ืžื ืกื” ืœืคืชื•ืจ. ื™ื™ืฉื•ืžื™ื ืจื‘ื™ื ื”ืคื•ืขืœื™ื ื‘ืžืจื›ื–ื™ ื ืชื•ื ื™ื ื›ื™ื•ื ืžืชืจื—ื‘ื™ื ืœืฆืจื•ืš ื›ืžื•ื™ื•ืช ื’ื“ื•ืœื•ืช ืฉืœ ืžืฉืื‘ื™ื. ืงื—ื• ืœืžืฉืœ ืœืžื™ื“ืช ืžื›ื•ื ื”, ื”ืžืฉืชืžืฉืช ื‘ืžืกืคืจ ืขืฆื•ื ืฉืœ ืฆืžืชื™ ืžื—ืฉื•ื‘. ืื‘ืœ ื›ืฉืื ื—ื ื• ืžื“ื‘ืจื™ื ืขืœ ื”ืืฆื”, ืื ื—ื ื• ืฆืจื™ื›ื™ื ืœื—ืฉื•ื‘ ืœื ืจืง ืขืœ ื”ืืฆืช ื”ืžื—ืฉื•ื‘, ืืœื ื’ื ืขืœ ื”ืืฆืช ื”ืชืฉืชื™ื•ืช".

ืœื“ื•ื’ืžื”, ื‘ืกื•ื’ ืฉืœ ืคืขื•ืœื•ืช ืœืžื™ื“ืช ืžื›ื•ื ื” ืฉื—ืงืจ ื‘ื•ืœืกื ืก ื‘ืคื•ืขืœ, ื›-50% ืžื”ื–ืžืŸ ืžื•ืฉืงืข ื‘ื”ืขื‘ืจืช ื ืชื•ื ื™ื ื”ืœื•ืš ื•ืฉื•ื‘ ื‘ื™ืŸ ื›ื•ื— ืžื—ืฉื•ื‘ ืžืคื•ื–ืจ, ื•ืจืง ืืช ืžื—ืฆื™ืช ื”ื–ืžืŸ ื”ื ื•ืชืจ ืžื•ืฉืงืข ื‘ื—ื™ืฉื•ื‘ื™ื ืขืฆืžื.

"ื–ื” ื”ืžืงื•ื ืฉื‘ื• ืื ื™ ื—ื•ืฉื‘ ืฉ-FPGA ื™ื›ื•ืœ ืœืขื–ื•ืจ, ื›ื™ ืื ื—ื ื• ื™ื›ื•ืœื™ื ืœื”ื‘ื˜ื™ื— ืฉื’ื ื”ื”ื™ื‘ื˜ื™ื ื”ื—ื™ืฉื•ื‘ื™ื™ื ื•ื”ืชืงืฉื•ืจืชื™ื™ื ืฉืœ ื”ืืคืœื™ืงืฆื™ื” ื™ื”ื™ื• ืื•ืคื˜ื™ืžืœื™ื™ื. ื•ืื ื—ื ื• ื™ื›ื•ืœื™ื ืœืขืฉื•ืช ื–ืืช ื‘ืจืžืช ื”ืชืฉืชื™ืช ื”ื›ื•ืœืœืช, ื•ื‘ืจืžืช ื”ืฉื‘ื‘ื™ื. ื–ื”ื• ืื—ื“ ื”ื™ืชืจื•ื ื•ืช ื”ื’ื“ื•ืœื™ื ืฉืœ FPGAs, ื”ืžืืคืฉืจ ืœืš ืœื™ืฆื•ืจ ืจืฉืชื•ืช ืชืงืฉื•ืจืช ืœืฆืจื›ื™ ื™ื™ืฉื•ืžื™ื ืกืคืฆื™ืคื™ื™ื. ื‘ื”ืชื‘ืกืก ืขืœ ื“ืคื•ืกื™ื ื˜ื™ืคื•ืกื™ื™ื ืฉืœ ืชื ื•ืขืช ื ืชื•ื ื™ื ื‘ืขื•ืžืกื™ ืขื‘ื•ื“ื” ืฉืœ AI, ืื ื™ ืœื ืจื•ืื” ืฆื•ืจืš ื‘ืืจื›ื™ื˜ืงื˜ื•ืจื” ืžื•ืจื›ื‘ืช ืžื‘ื•ืกืกืช ืžืชื’ื™ื. ืืชื” ื™ื›ื•ืœ ืœื‘ื ื•ืช ืจืฉืช ืขื ื–ืจื™ืžืช ื ืชื•ื ื™ื ื’ื“ื•ืœื”. ื›ืš ื’ื ืœื’ื‘ื™ ืžืฉื™ืžื•ืช ืื™ืžื•ืŸ ื‘ืจืฉืช ืขืฆื‘ื™ืช - ื ื™ืชืŸ ืœื‘ื ื•ืช ืจืฉืช ืจืฉืช ืขื ื’ื“ืœื™ ืžื ื•ืช ื”ืžื•ืชืืžื™ื ืœืžืฉื™ืžื” ืกืคืฆื™ืคื™ืช. ื‘ืืžืฆืขื•ืช FPGA, ืคืจื•ื˜ื•ืงื•ืœื™ ื”ืขื‘ืจืช ื ืชื•ื ื™ื ื•ื˜ื•ืคื•ืœื•ื’ื™ื•ืช ืžืขื’ืœื™ื ื ื™ืชื ื™ื ืœืงื ื” ืžื™ื“ื” ืžื“ื•ื™ืง ืžืื•ื“ ื•ืœื”ืชืื™ื ืœื™ื™ืฉื•ื ืกืคืฆื™ืคื™. ื•ื‘ืžืงืจื” ืฉืœ ืœืžื™ื“ืช ืžื›ื•ื ื”, ื‘ืจื•ืจ ื’ื ืฉืื ื—ื ื• ืœื ืฆืจื™ื›ื™ื ืžืกืคืจื™ ื ืงื•ื“ื” ืฆืคื” ืขื ื“ื™ื•ืง ื›ืคื•ืœ, ื•ืื ื—ื ื• ื™ื›ื•ืœื™ื ืœื”ืชืื™ื ื’ื ืืช ื–ื”".

ื”ื”ื‘ื“ืœ ื‘ื™ืŸ FPGA ืœ-CPU ืื• ASIC ืžื•ืชืื ืื™ืฉื™ืช ื”ื•ื ืฉื”ืื—ืจื•ื ื™ื ืžืชื•ื›ื ืชื™ื ื‘ืžืคืขืœ, ื•ืœืื—ืจ ืžื›ืŸ ืื™ื ืš ื™ื›ื•ืœ ืขื•ื“ ืœืฉื ื•ืช ืืช ื“ืขืชืš ืœื’ื‘ื™ ืกื•ื’ื™ ื”ื ืชื•ื ื™ื ื”ืžื—ื•ืฉื‘ื™ื ืื• ื”ืืœืžื ื˜ื™ื ื”ืžื—ื•ืฉื‘ื™ื, ืื• ืœื’ื‘ื™ ืื•ืคื™ ื”ื ืชื•ื ื™ื. ืœื–ืจื•ื ื“ืจืš ื”ืžื›ืฉื™ืจ. FPGAs ืžืืคืฉืจื™ื ืœืš ืœืฉื ื•ืช ืืช ื“ืขืชืš ืื ืชื ืื™ ื”ื”ืคืขืœื” ืžืฉืชื ื™ื.

ื‘ืขื‘ืจ, ื”ื™ืชืจื•ืŸ ื”ื–ื” ื”ื™ื” ื‘ืขืœ ืžื—ื™ืจ, ื›ืืฉืจ ืชื›ื ื•ืช FPGA ืœื ื”ื™ื” ืœื‘ืขืœื™ ืœื‘ ื—ืœืฉ. ื”ืฆื•ืจืš ื”ื•ื ืœืคืชื•ื— ืžื”ื“ืจื™ื ืฉืœ FPGA ื›ื“ื™ ืœื”ืฉืชืœื‘ ื˜ื•ื‘ ื™ื•ืชืจ ืขื ื”ื›ืœื™ื ืฉืžืชื›ื ืชื™ื ืžืฉืชืžืฉื™ื ื‘ื”ื ื›ื“ื™ ืœื›ืชื•ื‘ ื™ื™ืฉื•ืžื™ื ืžืงื‘ื™ืœื™ื ืœืžืขื‘ื“ ื‘-C, C++ ืื• Python, ื•ืœื”ืขื‘ื™ืจ ื—ืœืง ืžื”ืขื‘ื•ื“ื” ืœืžื™ืงื•ืจ ื—ื•ืฅ ืœืกืคืจื™ื•ืช ืฉืžืื™ืฆื•ืช ื ื”ืœื™ื ื‘-FPGA. ื–ื” ืžื” ืฉืขื•ืฉื” ืžื—ืกื ื™ืช ื”ืœืžื™ื“ื” ื”ืžื›ื•ื ื” ืฉืœ Vitis, ื”ืžื ื™ืขื” ืคืœื˜ืคื•ืจืžื•ืช ML ื›ืžื• Caffe ื•-TensorFlow, ืขื ืกืคืจื™ื•ืช ืœื”ืคืขืœืช ืžื•ื“ืœื™ื AI ืงื•ื ื‘ื ืฆื™ื•ื ืœื™ื™ื ืื• ื”ื•ืกืคืช ื™ื›ื•ืœื•ืช FPGA ืœืžืฉื™ืžื•ืช ื›ืžื• ื”ืžืจืช ืงื™ื“ื•ื“ ื•ื™ื“ืื•, ื–ื™ื”ื•ื™ ืื•ื‘ื™ื™ืงื˜ื™ ื•ื™ื“ืื• ื•ื ื™ืชื•ื— ื ืชื•ื ื™ื. , ื ื™ื”ื•ืœ ืกื™ื›ื•ื ื™ื ืคื™ื ื ืกื™ื™ื ื•ื›ืœ ืฉืœื™ืฉื™ื” -ืกืคืจื™ื•ืช ืžืคืœื’ื•ืช.

ื”ืงื•ื ืกืคื˜ ื”ื–ื” ืื™ื ื• ืฉื•ื ื” ื‘ื”ืจื‘ื” ืžืคืจื•ื™ืงื˜ CUDA ืฉืœ Nvidia, ืฉื”ื•ืฉืง ืœืคื ื™ ืขืฉื•ืจ, ืืฉืจ ืžื•ืจื™ื“ ืžื—ืฉื•ื‘ ืžืงื‘ื™ืœ ืœืžืื™ืฆื™ GPU, ืื• ืžืขืจืš ื”ื›ืœื™ื ROCm ืฉืœ AMD, ืื• ืžื”ื”ื‘ื˜ื—ื” ืฉืœ ืคืจื•ื™ืงื˜ OneAPI ืฉืœ ืื™ื ื˜ืœ, ืฉืืžื•ืจ ืœืจื•ืฅ ืขืœ ืžืขื‘ื“ื™ื, GPUs ื•-FPGA ืฉื•ื ื™ื.

ื”ืฉืืœื” ื”ื™ื—ื™ื“ื” ื”ื™ื ื›ื™ืฆื“ ื›ืœ ื”ื›ืœื™ื ื”ืœืœื• ื™ื—ื•ื‘ืจื• ื™ื—ื“ ื›ืš ืฉื›ืœ ืื“ื ื™ื•ื›ืœ ืœืชื›ื ืช ืกื˜ ืฉืœ ื›ื•ื—ื•ืช ืžื—ืฉื•ื‘ ืœืคื™ ืฉื™ืงื•ืœ ื“ืขืชื•. ื–ื” ื—ืฉื•ื‘ ื›ื™ FPGAs ื”ืคื›ื• ืžื•ืจื›ื‘ื™ื ื™ื•ืชืจ, ื”ืจื‘ื” ื™ื•ืชืจ ืžื•ืจื›ื‘ื™ื ืžื›ืœ ื”ืžืขื‘ื“ื™ื ื”ื–ืžื™ื ื™ื. ื”ื ืžื™ื•ืฆืจื™ื ื‘ืชื”ืœื™ื›ื™ ื”ื™ื™ืฆื•ืจ ื”ืžืชืงื“ืžื™ื ื‘ื™ื•ืชืจ ื•ื‘ื˜ื›ื ื•ืœื•ื’ื™ื•ืช ืืจื™ื–ืช ื”ืฉื‘ื‘ื™ื ื”ืžื•ื“ืจื ื™ื•ืช ื‘ื™ื•ืชืจ. ื•ื”ื ื™ืžืฆืื• ืืช ื”ื ื™ืฉื” ืฉืœื”ื, ื›ื™ ืื ื—ื ื• ื›ื‘ืจ ืœื ื™ื›ื•ืœื™ื ืœื‘ื–ื‘ื– ื–ืžืŸ, ื›ืกืฃ, ืื ืจื’ื™ื” ื•ืื™ื ื˜ืœื™ื’ื ืฆื™ื” - ื›ืœ ืืœื” ื”ื ืžืฉืื‘ื™ื ื™ืงืจื™ื ืžื“ื™.

"ืจื›ื™ื‘ื™ FPGA ืžืฆื™ืขื™ื ื™ืชืจื•ื ื•ืช ื˜ื›ื ื•ืœื•ื’ื™ื™ื", ืื•ืžืจ ื‘ื•ืœืกื ืก. - ื•ื–ื” ืœื ืจืง ื”ืคืจืกื•ื ื”ืจื’ื™ืœ ืขืœ ื”ืชืืžื” ื•ื”ืชืืžื” ืžื—ื“ืฉ. ื‘ื›ืœ ื”ื™ื™ืฉื•ืžื™ื ื”ื—ืฉื•ื‘ื™ื - ืœืžื™ื“ืช ืžื›ื•ื ื”, ื ื™ืชื•ื— ื’ืจืคื™ื, ืžืกื—ืจ ื‘ืžื”ื™ืจื•ืช ื’ื‘ื•ื”ื” ื•ื›ื•'. - ื™ืฉ ืœื”ื ืืช ื”ื™ื›ื•ืœืช ืœื”ืชืื™ื ืœืžืฉื™ืžื” ืกืคืฆื™ืคื™ืช ืœื ืจืง ืืช ื ืชื™ื‘ ื”ืคืฆืช ื”ื ืชื•ื ื™ื, ืืœื ื’ื ืืช ืืจื›ื™ื˜ืงื˜ื•ืจืช ื”ื–ื™ื›ืจื•ืŸ - ืื™ืš ื ืชื•ื ื™ื ื–ื–ื™ื ื‘ืชื•ืš ื”ืฉื‘ื‘. ืœืจื›ื™ื‘ื™ FPGA ื™ืฉ ื’ื ื”ืจื‘ื” ื™ื•ืชืจ ื–ื™ื›ืจื•ืŸ ืžื•ื‘ื ื” ืžืžื›ืฉื™ืจื™ื ืื—ืจื™ื. ื›ืžื• ื›ืŸ, ื™ืฉ ืœืงื—ืช ื‘ื—ืฉื‘ื•ืŸ ืฉืื ืžืฉื™ืžื” ืื™ื ื” ืžืชืื™ืžื” ืœ-FPGA ืื—ื“, ืืชื” ื™ื›ื•ืœ ืœืฉื ื•ืช ืื•ืชื” ืขืœ ืคื ื™ ืžืกืคืจ ืฉื‘ื‘ื™ื ืžื‘ืœื™ ืœื”ื™ืชืงืœ ื‘ื—ืกืจื•ื ื•ืช ืฉืžื—ื›ื™ื ืœืš ื‘ืขืช ืฉื™ื ื•ื™ ืงื ื” ืžื™ื“ื” ืฉืœ ืžืฉื™ืžื•ืช ืขืœ ืคื ื™ ืžืกืคืจ ืžืขื‘ื“ื™ื ืื• GPUs."

ืžืงื•ืจ: www.habr.com

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