MIPS Technologies ืžืคืกื™ืงื” ืืช ืคื™ืชื•ื— ืืจื›ื™ื˜ืงื˜ื•ืจืช MIPS ืœื˜ื•ื‘ืช RISC-V

MIPS Technologies ืžืคืกื™ืงื” ืืช ื”ืคื™ืชื•ื— ืฉืœ ืืจื›ื™ื˜ืงื˜ื•ืจืช MIPS ื•ืขื•ื‘ืจืช ืœื™ืฆื™ืจืช ืžืขืจื›ื•ืช ื”ืžื‘ื•ืกืกื•ืช ืขืœ ืืจื›ื™ื˜ืงื˜ื•ืจืช RISC-V. ื”ื•ื—ืœื˜ ืœื‘ื ื•ืช ืืช ื”ื“ื•ืจ ื”ืฉืžื™ื ื™ ืฉืœ ืืจื›ื™ื˜ืงื˜ื•ืจืช MIPS ืขืœ ื”ืคื™ืชื•ื—ื™ื ืฉืœ ืคืจื•ื™ืงื˜ ื”ืงื•ื“ ื”ืคืชื•ื— RISC-V.

ื‘ืฉื ืช 2017, MIPS Technologies ืขื‘ืจื” ืœืฉืœื™ื˜ืช Wave Computing, ืกื˜ืืจื˜-ืืค ื”ืžื™ื™ืฆืจ ืžืื™ืฆื™ื ืœืžืขืจื›ื•ืช ืœืžื™ื“ืช ืžื›ื•ื ื” ื‘ืืžืฆืขื•ืช ืžืขื‘ื“ื™ MIPS. ื‘ืฉื ื” ืฉืขื‘ืจื” ื”ื—ืœื” Wave Computing ื‘ื”ืœื™ืš ืคืฉื™ื˜ืช ื”ืจื’ืœ, ืืš ืœืคื ื™ ืฉื‘ื•ืข, ื‘ื”ืฉืชืชืคื•ืช ืงืจืŸ ื”ืกื™ื›ื•ืŸ Tallwood, ื”ื™ื ื™ืฆืื” ืžืคืฉื™ื˜ืช ืจื’ืœ, ื”ืชืืจื’ื ื” ืžื—ื“ืฉ ื•ื ื•ืœื“ื” ืžื—ื“ืฉ ื‘ืฉื ื—ื“ืฉ - MIPS. ื—ื‘ืจืช MIPS ื”ื—ื“ืฉื” ืฉื™ื ืชื” ืœื—ืœื•ื˜ื™ืŸ ืืช ื”ืžื•ื“ืœ ื”ืขืกืงื™ ืฉืœื” ื•ืœื ืชื”ื™ื” ืžื•ื’ื‘ืœืช ืœืžืขื‘ื“ื™ื.

ื‘ืขื‘ืจ, MIPS Technologies ื”ื™ื™ืชื” ืžืขื•ืจื‘ืช ื‘ืคื™ืชื•ื— ืื“ืจื™ื›ืœื™ ื•ืจื™ืฉื•ื™ ืงื ื™ื™ืŸ ืจื•ื—ื ื™ ื”ืงืฉื•ืจ ืœืžืขื‘ื“ื™ MIPS, ืžื‘ืœื™ ืœืขืกื•ืง ื™ืฉื™ืจื•ืช ื‘ื™ื™ืฆื•ืจ. ื”ื—ื‘ืจื” ื”ื—ื“ืฉื” ืชื™ื™ืฆืจ ืฉื‘ื‘ื™ื, ืืš ืžื‘ื•ืกืกืช ืขืœ ืืจื›ื™ื˜ืงื˜ื•ืจืช RISC-V. MIPS ื•-RISC-V ื“ื•ืžื™ื ื‘ืชืคื™ืกื” ื•ื‘ืคื™ืœื•ืกื•ืคื™ื”, ืืš RISC-V ืคื•ืชื— ืขืœ ื™ื“ื™ ืืจื’ื•ืŸ ืœืœื ืžื˜ืจื•ืช ืจื•ื•ื— RISC-V International ืขื ืชืจื•ืžื•ืช ืงื”ื™ืœืชื™ื•ืช. MIPS ื”ื—ืœื™ื˜ื” ืœื ืœื”ืžืฉื™ืš ื•ืœืคืชื— ืืจื›ื™ื˜ืงื˜ื•ืจื” ืžืฉืœื”, ืืœื ืœื”ืฆื˜ืจืฃ ืœืฉื™ืชื•ืฃ ื”ืคืขื•ืœื”. ืจืื•ื™ ืœืฆื™ื™ืŸ ื›ื™ MIPS Technologies ื›ื‘ืจ ื–ืžืŸ ืจื‘ ื—ื‘ืจื” ื‘-RISC-V International, ื•ื”-CTO ืฉืœ RISC-V International ื”ื•ื ืขื•ื‘ื“ ืœืฉืขื‘ืจ ืฉืœ MIPS Technologies.

ื ื–ื›ื™ืจ ื›ื™ RISC-V ืžืกืคืงืช ืžืขืจื›ืช ื”ื•ืจืื•ืช ืžื›ื•ื ื” ืคืชื•ื—ื” ื•ื’ืžื™ืฉื” ื”ืžืืคืฉืจืช ืœื‘ื ื•ืช ืžื™ืงืจื•-ืžืขื‘ื“ื™ื ืขื‘ื•ืจ ื™ื™ืฉื•ืžื™ื ืฉืจื™ืจื•ืชื™ื™ื ืžื‘ืœื™ ืœื“ืจื•ืฉ ืชืžืœื•ื’ื™ื ืื• ืœื”ื˜ื™ืœ ืชื ืื™ื ืœืฉื™ืžื•ืฉ. RISC-V ืžืืคืฉืจ ืœืš ืœื™ืฆื•ืจ SoCs ื•ืžืขื‘ื“ื™ื ืคืชื•ื—ื™ื ืœื—ืœื•ื˜ื™ืŸ. ื ื›ื•ืŸ ืœืขื›ืฉื™ื•, ื‘ื”ืชื‘ืกืก ืขืœ ืžืคืจื˜ RISC-V, ื—ื‘ืจื•ืช ื•ืงื”ื™ืœื•ืช ืฉื•ื ื•ืช ืชื—ืช ืจื™ืฉื™ื•ื ื•ืช ื—ื•ืคืฉื™ื™ื ืฉื•ื ื™ื (BSD, MIT, Apache 2.0) ืžืคืชื—ื•ืช ื›ืžื” ืขืฉืจื•ืช ื’ืจืกืื•ืช ืฉืœ ืœื™ื‘ื•ืช ืžื™ืงืจื•-ืžืขื‘ื“, SoC ื•ืฉื‘ื‘ื™ื ืฉื›ื‘ืจ ืžื™ื•ืฆืจื™ื. ืชืžื™ื›ืช RISC-V ืงื™ื™ืžืช ืžืื– ื”ื”ืคืฆื•ืช ืฉืœ Glibc 2.27, binutils 2.30, gcc 7 ื•ืœื™ื‘ืช ืœื™ื ื•ืงืก 4.15.

ืžืงื•ืจ: OpenNet.ru

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