HPVM 2.0, ืžื”ื“ืจ ืขื‘ื•ืจ CPU, GPU, FPGA ื•ืžืื™ืฆื™ ื—ื•ืžืจื” ืคื•ืจืกื

ืคืจื•ื™ืงื˜ LLVM ื”ืฆื™ื’ ืืช ืฉื—ืจื•ืจื• ืฉืœ ืžื”ื“ืจ HPVM 2.0 (Heterogeneous Parallel Virtual Machine), ืฉืžื˜ืจืชื• ืœืคืฉื˜ ืืช ื”ืชื›ื ื•ืช ืขื‘ื•ืจ ืžืขืจื›ื•ืช ื”ื˜ืจื•ื’ื ื™ื•ืช ื•ืœืกืคืง ื›ืœื™ื ืœื”ืคืงืช ืงื•ื“ ืขื‘ื•ืจ CPUs, GPUs, FPGAs ื•ืžืื™ืฆื™ ื—ื•ืžืจื” ืกืคืฆื™ืคื™ื™ื ืœืชื—ื•ื. ืงื•ื“ ื”ืคืจื•ื™ืงื˜ ืžื•ืคืฅ ืชื—ืช ืจื™ืฉื™ื•ืŸ Apache 2.0.

ืชื›ื ื•ืช ืขื‘ื•ืจ ืžืขืจื›ื•ืช ืžืงื‘ื™ืœื•ืช ื”ื˜ืจื•ื’ื ื™ื•ืช ืžืกื•ื‘ืš ื‘ืฉืœ ื”ื™ืžืฆืื•ืช ื‘ืžืขืจื›ืช ืื—ืช ืฉืœ ืจื›ื™ื‘ื™ื ื”ืžืฉืชืžืฉื™ื ื‘ืžื•ื“ืœื™ื ืฉื•ื ื™ื ืœื”ืฉื’ืช ืžืงื‘ื™ืœื™ื•ืช (ืœื™ื‘ื•ืช CPU, ื”ื•ืจืื•ืช ื•ืงื˜ื•ืจื™ื•ืช, GPUs ื•ื›ื•'), ืงื‘ื•ืฆื•ืช ืฉื•ื ื•ืช ืฉืœ ื”ื•ืจืื•ืช ื•ื”ื™ืจืจื›ื™ื•ืช ื–ื™ื›ืจื•ืŸ ืฉื•ื ื•ืช. ื›ืœ ืžืขืจื›ืช ืžืฉืชืžืฉืช ื‘ืฉื™ืœื•ื‘ ืžืฉืœื” ืฉืœ ืจื›ื™ื‘ื™ื ืืœื”. ื”ืจืขื™ื•ืŸ ื”ืžืจื›ื–ื™ ืฉืœ ืคืจื•ื™ืงื˜ HPVM ื”ื•ื ืœื”ืฉืชืžืฉ ื‘ื”ืจื›ื‘ืช ื™ื™ืฆื•ื’ ืžืื•ื—ื“ ืฉืœ ืชื•ื›ื ื™ื•ืช ืžืงื‘ื™ืœื•ืช ืฉื™ื›ื•ืœื•ืช ืœืฉืžืฉ ืขื‘ื•ืจ ืกื•ื’ื™ื ืฉื•ื ื™ื ืฉืœ ื—ื•ืžืจื” ื”ืชื•ืžื›ืช ื‘ืžื—ืฉื•ื‘ ืžืงื‘ื™ืœื™, ื›ื•ืœืœ GPUs, ื”ื•ืจืื•ืช ื•ืงื˜ื•ืจื™ื•ืช, ืžืขื‘ื“ื™ื ืžืจื•ื‘ื™ ืœื™ื‘ื•ืช, FPGAs ื•ืžื’ื•ื•ืŸ ืžื™ื•ื—ื“ื™ื. ืฉื‘ื‘ื™ ืžืื™ืฅ.

ื‘ื ื™ื’ื•ื“ ืœืžืขืจื›ื•ืช ืื—ืจื•ืช, HPVM ื ื™ืกืชื” ืœืฉืœื‘ ืฉืœื•ืฉ ืืคืฉืจื•ื™ื•ืช ืœืืจื’ื•ืŸ ืžื—ืฉื•ื‘ ื”ื˜ืจื•ื’ื ื™ - ื™ื™ืฆื•ื’ ื‘ื™ื ื™ื™ื (IR), ืืจื›ื™ื˜ืงื˜ื•ืจืช ืขืจื›ืช ื”ื•ืจืื•ืช ื•ื™ืจื˜ื•ืืœื™ืช (V-ISA), ื•ืชื–ืžื•ืŸ ื–ืžืŸ ืจื™ืฆื”, ืœืœื ืชืœื•ืช ื‘ืฉืคืช ื”ืชื›ื ื•ืช ื•ื‘ืฆื™ื•ื“:

  • ื™ื™ืฆื•ื’ ื‘ื™ื ื™ื™ื HPVM ืžืจื—ื™ื‘ ืืช ื™ื™ืฆื•ื’ ื”ื‘ื™ื ื™ื™ื ืฉืœ ื”ื•ืจืื•ืช LLVM ืขืœ ื™ื“ื™ ืฉื™ืžื•ืฉ ื‘ื’ืจืฃ ื–ืจื™ืžืช ื ืชื•ื ื™ื ื”ื™ืจืจื›ื™ ื›ื“ื™ ืœืœื›ื•ื“ ืžืงื‘ื™ืœื™ื•ืช ื‘ืจืžืช ื”ืžืฉื™ืžื•ืช, ื”ื ืชื•ื ื™ื ื•ื”ืฆื™ื ื•ืจื•ืช ื”ื—ื™ืฉื•ื‘ื™ื™ื. ื™ื™ืฆื•ื’ ื”ื‘ื™ื ื™ื™ื ืฉืœ HPVM ื›ื•ืœืœ ื’ื ื”ื•ืจืื•ืช ื•ืงื˜ื•ืจื™ื•ืช ื•ื–ื™ื›ืจื•ืŸ ืžืฉื•ืชืฃ. ื”ืžื˜ืจื” ื”ืขื™ืงืจื™ืช ืฉืœ ืฉื™ืžื•ืฉ ื‘ื™ื™ืฆื•ื’ ื‘ื™ื ื™ื™ื ื”ื™ื ื™ืฆื™ืจืช ืงื•ื“ ื™ืขื™ืœ ื•ืื•ืคื˜ื™ืžื™ื–ืฆื™ื” ืขื‘ื•ืจ ืžืขืจื›ื•ืช ื”ื˜ืจื•ื’ื ื™ื•ืช.
  • ืืจื›ื™ื˜ืงื˜ื•ืจืช ืขืจื›ืช ื”ื•ืจืื•ืช ื•ื™ืจื˜ื•ืืœื™ืช (V-ISA) ืžืคืฉื˜ืช ื—ื•ืžืจื” ื‘ืจืžื” ื ืžื•ื›ื” ื•ืžืื—ื“ืช ืฆื•ืจื•ืช ืฉื•ื ื•ืช ืฉืœ ืžืงื‘ื™ืœื™ื•ืช ื•ืืจื›ื™ื˜ืงื˜ื•ืจื•ืช ื–ื™ื›ืจื•ืŸ ืชื•ืš ืฉื™ืžื•ืฉ ืจืง ื‘ืžื•ื“ืœ ื”ืžืงื‘ื™ืœื™ื•ืช ื”ื‘ืกื™ืกื™, ื’ืจืฃ ื–ืจื™ืžืช ื”ื ืชื•ื ื™ื. V-ISA ืžืืคืฉืจ ืœื”ืฉื™ื’ ื ื™ื™ื“ื•ืช ื‘ื™ืŸ ืกื•ื’ื™ื ืฉื•ื ื™ื ืฉืœ ื—ื•ืžืจื” ืœืžื—ืฉื•ื‘ ืžืงื‘ื™ืœ ื•ืžืืคืฉืจืช ืœื ืœืื‘ื“ ื‘ื™ืฆื•ืขื™ื ื‘ืขืช ืฉื™ืžื•ืฉ ื‘ืืœืžื ื˜ื™ื ืฉื•ื ื™ื ืฉืœ ืžืขืจื›ื•ืช ื”ื˜ืจื•ื’ื ื™ื•ืช. ื ื™ืชืŸ ืœื”ืฉืชืžืฉ ื‘-Virtual ISA ื’ื ื›ื“ื™ ืœืกืคืง ืงื•ื“ ื”ืคืขืœื” ื’ื ืจื™ ืฉืœ ืชื•ื›ื ื™ื•ืช ืฉื™ื›ื•ืœ ืœืจื•ืฅ ืขืœ CPUs, GPUs, FPGAs ื•ืžืื™ืฆื™ื ืฉื•ื ื™ื.
  • ืžื“ื™ื ื™ื•ืช ืชื–ืžื•ืŸ ื’ืžื™ืฉื” ืฉืœ ืชื”ืœื™ื›ื™ ืžื—ืฉื•ื‘ ืžื™ื•ืฉืžื•ืช ื‘ื–ืžืŸ ืจื™ืฆื” ื•ืžื™ื•ืฉืžื•ืช ื”ืŸ ืขืœ ื‘ืกื™ืก ืžื™ื“ืข ืขืœ ื”ืชื•ื›ื ื™ืช (ืžื‘ื ื” ื”ื’ืจืฃ) ื•ื”ืŸ ืขืœ ื™ื“ื™ ื”ื™ื“ื•ืจ ืฆืžืชื™ ืชื•ื›ื ื™ืช ื‘ื•ื“ื“ื™ื ืœื‘ื™ืฆื•ืข ื‘ื›ืœ ืื—ื“ ืžื”ืชืงื ื™ ืžื—ืฉื•ื‘ ื”ื™ืขื“ ื”ื–ืžื™ื ื™ื ื‘ืžืขืจื›ืช.

ืžื—ื•ืœืœื™ ื”ืงื•ื“ ืฉืคื•ืชื—ื• ืขืœ ื™ื“ื™ ื”ืคืจื•ื™ืงื˜ ืžืกื•ื’ืœื™ื ืœืชืจื’ื ืฆืžืชื™ ื™ื™ืฉื•ืžื™ื ืฉื”ื•ื’ื“ืจื• ื‘ืืžืฆืขื•ืช ISA ื•ื™ืจื˜ื•ืืœื™ ืœื‘ื™ืฆื•ืข ื‘ืืžืฆืขื•ืช NVIDIA GPUs (cuDNN ื•-OpenCL), ื”ื•ืจืื•ืช ื•ืงื˜ื•ืจ ืื™ื ื˜ืœ AVX, FPGAs ื•ืžืขื‘ื“ื™ x86 ืžืจื•ื‘ื™ ืœื™ื‘ื•ืช. ื™ืฆื•ื™ืŸ ื›ื™ ื‘ื™ืฆื•ืขื™ ื”ืชื•ืฆืื•ืช ืฉืœ ืžืชืจื’ืžื™ HPVM ื“ื•ืžื™ื ืœืงื•ื“ OpenCL ืฉื ื›ืชื‘ ื‘ืื•ืคืŸ ื™ื“ื ื™ ืขื‘ื•ืจ GPUs ื•ื”ืชืงื ื™ ืžื—ืฉื•ื‘ ื•ืงื˜ื•ืจื™ื™ื.

ื”ื—ื™ื“ื•ืฉื™ื ื”ืขื™ืงืจื™ื™ื ืฉืœ HPVM 2.0:

  • ืžื•ืฆืข ื—ื–ื™ืช ื”ืฉืคื” Hetero-C++, ืืฉืจ ืžืคืฉื˜ืช ืืช ื”ื”ืงื‘ืœื” ืฉืœ ืงื•ื“ ื™ื™ืฉื•ื C/C++ ืœื”ื™ื“ื•ืจ ื‘-HPVM. Hetero-C++ ืžื’ื“ื™ืจ ื”ืจื—ื‘ื•ืช ืขื‘ื•ืจ ืžืงื‘ื™ืœื™ื•ืช ื‘ืจืžืช ื”ื ืชื•ื ื™ื ื•ืžืฉื™ืžื•ืช ื”ื™ืจืจื›ื™ื•ืช ื”ืžืžื•ืคื•ืช ืœื’ืจืคื™ ื—ื•ื˜ ืฉืœ HPVM.
  • FPGA backend ื ื•ืกืฃ ื›ื“ื™ ืœืชืžื•ืš ื‘ื‘ื™ืฆื•ืข ืงื•ื“ ื‘-Intel FPGA. ื›ื“ื™ ืœืืจื’ืŸ ืืช ื”ื‘ื™ืฆื•ืข, ื ืขืฉื” ืฉื™ืžื•ืฉ ื‘-Intel FPGA SDK ืขื‘ื•ืจ OpenCL.
  • ื ื•ืกืคื” ืžืกื’ืจืช ื”-DSE (Design Space Exploration), ื”ื›ื•ืœืœืช ืื•ืคื˜ื™ืžื™ื–ืฆื™ื•ืช ืžื”ื“ืจ ื•ืžื ื’ื ื•ื ื™ ื–ื™ื”ื•ื™ ืฆื•ื•ืืจื™ ื‘ืงื‘ื•ืง ืœื›ื•ื•ื ื•ืŸ ืื•ื˜ื•ืžื˜ื™ ืฉืœ ื™ื™ืฉื•ืžื™ื ืขื‘ื•ืจ ืคืœื˜ืคื•ืจืžืช ื—ื•ืžืจื” ื ืชื•ื ื”. ื”ืžืกื’ืจืช ืžื›ื™ืœื” ืžื•ื“ืœ ื‘ื™ืฆื•ืขื™ื ืžื•ื›ืŸ ืขื‘ื•ืจ FPGA ืžื‘ื™ืช ืื™ื ื˜ืœ ื•ืžืืคืฉืจืช ืœืš ืœื—ื‘ืจ ืžืขื‘ื“ื™ื ืžืฉืœืš ืœืฆื•ืจืš ืื•ืคื˜ื™ืžื™ื–ืฆื™ื” ืขื‘ื•ืจ ื›ืœ ืžื›ืฉื™ืจ ืฉื ืชืžืš ืขืœ ื™ื“ื™ HPVM. ื ื™ืชืŸ ืœื”ื—ื™ืœ ืื•ืคื˜ื™ืžื™ื–ืฆื™ื•ืช ื”ืŸ ื‘ืจืžืช ื’ืจืฃ ื–ืจื™ืžืช ื”ื ืชื•ื ื™ื ืฉืœ HPVM ื•ื”ืŸ ื‘ืจืžืช LLVM.
  • ืจื›ื™ื‘ื™ LLVM ืขื•ื“ื›ื ื• ืœื’ืจืกื” 13.0.
  • ื”ืงื•ื“ ืื•ืจื’ืŸ ืžื—ื“ืฉ ื›ื“ื™ ืœื”ืงืœ ืขืœ ื”ื ื™ื•ื•ื˜ ื‘ื™ืŸ ื‘ืกื™ืก ื”ืงื•ื“, ื”ืกืคืจื™ื•ืช ื•ื›ืœื™ ื”ืฉื™ืจื•ืช.
  • ืชืฉืชื™ืช ื”ื‘ื“ื™ืงื•ืช ืฉื•ืคืจื”, ื ื•ืกืคื• ื‘ื“ื™ืงื•ืช ื—ื“ืฉื•ืช ืœืจื›ื™ื‘ื™ HPVM ืฉื•ื ื™ื.

ืžืงื•ืจ: OpenNet.ru

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