ืžืงื•ืจื•ืช ืฉืœ ืœื™ื‘ื•ืช MIPS32 microAptiv ืฉืคื•ืจืกืžื• ืชื—ืช ืชื•ื›ื ื™ืช MIPS Open

Wave Computing (Wave Computing, ืœืฉืขื‘ืจ MIPS Technologies, ืฉื ืจื›ืฉื” ื‘ืขื‘ืจ ืขืœ ื™ื“ื™ Imagination Technologies ื•ืœืื—ืจ ืคื™ืจื•ืงื” ืฉื•ื‘ ืงื™ื‘ืœื” ืžืขืžื“ ืขืฆืžืื™) ื”ื•ื“ื™ืขื” ืขืœ ืคืจืกื•ื ืงื•ื“ ื”ืžืงื•ืจ ืœืœื™ื‘ื•ืช ืžืขื‘ื“ MIPS32 microAptiv ื‘ืžืกื’ืจืช ืชื•ื›ื ื™ืช MIPS Open.

ืงื•ื“ ืฉืคื•ืจืกื ืขื‘ื•ืจ ืฉืชื™ ืžื—ืœืงื•ืช ืฉืœ ื’ืจืขื™ื ื™ื:

  • ืœื™ื‘ืช microAptiv MCU ื”ื™ื ืœื™ื‘ืช ืžื™ืงืจื•-ื‘ืงืจ ืœืžืขืจื›ื•ืช ืžืฉื•ื‘ืฆื•ืช ื‘ื–ืžืŸ ืืžืช.
  • ืœื™ื‘ืช microAptiv MPU - ื›ื•ืœืœืช ื‘ืงืจ ืžื˜ืžื•ืŸ ื•ื™ื—ื™ื“ืช ื ื™ื”ื•ืœ ื–ื™ื›ืจื•ืŸ (MMU), ื”ืžืกืคืงืช ืืช ื”ื™ื›ื•ืœืช ืœื”ืคืขื™ืœ ืžืขืจื›ื•ืช ื”ืคืขืœื” ืžืœืื•ืช ื›ืžื• ืœื™ื ื•ืงืก.

ะ’ ืงื˜ืข ื”ื•ืจื“ื”:

  • ืžืกืžืš ืขื ืืจื›ื™ื˜ืงื˜ื•ืจืช MIPS Open
  • MIPS Open IDE (ื’ืจืกืื•ืช ืœื™ื ื•ืงืก ื•-Windows)
  • ื—ื‘ื™ืœื•ืช MIPS Open FPGA - ืœื”ืคืขืœืช ืœื™ื‘ื•ืช MIPS Open ืขืœ FPGAs
  • ืงื•ื“ ื”ืžืงื•ืจ ืฉืœ ืœื™ื‘ื•ืช microAptiv UP Core ื•-microAptiv UC Core ื‘ืฉืคืช ืชื™ืื•ืจ ื”ื—ื•ืžืจื” Verilog

ืœื”ื•ืจื“ื” ื™ืฉ โ€‹โ€‹ืœืงื‘ืœ ืืช ืชื ืื™ ื”ืกื›ื ื”ืจื™ืฉื™ื•ืŸ ื•ืœื”ื™ืจืฉื ื‘ืืชืจ.

ื‘ืขื‘ืจ Wave Computing ื”ื›ืจื™ื– ืขืœ ื”ืฉืงืช ื”ืชื•ื›ื ื™ืช MIPS ืคืชื•ื—, ืฉื‘ื• ื”ืžืฉืชืชืคื™ื ื™ื•ื›ืœื• ืœืฉื—ืจืจ ืœื™ื‘ื•ืช MIPS ืžืฉืœื”ื ืžื‘ืœื™ ืœืฉืœื ืขื‘ื•ืจ ืื™ืฉื•ืจ ืืจื›ื™ื˜ืงื˜ื•ืจื”, ืœืงื ื•ืช ืืช ืงื•ื“ ื”ืžืงื•ืจ ืฉืœ ื”ื’ืจืขื™ื ื™ื, ืœืฉืœื ื“ืžื™ ืจื™ืฉื™ื•ืŸ ืื—ืจื™ื, ื•ื’ื ืœืงื‘ืœ ื’ื™ืฉื” ืœืงื•ื“ ื”ืžืงื•ืจ ืฉืœ ื’ืจืขื™ื ื™ MIPS ืงื™ื™ืžื™ื ืฉืคื•ืชื—ื• ืขืœ ื™ื“ื™ Wave Computing.

ืžืงื•ืจ: linux.org.ru

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