ื”ืžื™ืงืจื•-ืืจื›ื™ื˜ืงื˜ื•ืจื” ื”ืคืชื•ื—ื” ืฉืœ MIPS R6 ืฉื•ื—ืจืจื”

ื‘ื“ืฆืžื‘ืจ ื”ืื—ืจื•ืŸ, Wave Computing, ืฉื”ืฉืชืœื˜ื” ืขืœ ื”ืขื™ืฆื•ื‘ื™ื ื•ื”ืคื˜ื ื˜ื™ื ืฉืœ MIPS Technologies ื‘ืขืงื‘ื•ืช ืคืฉื™ื˜ืช ื”ืจื’ืœ ืฉืœ Imagination Technologies, ื”ื•ื“ื™ืขื” ืขืœ ื›ื•ื•ื ืชื” ืœื”ืคื•ืš ืืช ืžืขืจืš ื”ื”ื•ืจืื•ืช, ื”ื›ืœื™ื ื•ื”ืืจื›ื™ื˜ืงื˜ื•ืจื” ืฉืœ MIPS 32-bit ื•-64-bit ืคืชื•ื— ื•ืœืœื ืชืžืœื•ื’ื™ื. Wave Computing ื”ื‘ื˜ื™ื—ื” ืœืกืคืง ื’ื™ืฉื” ืœื—ื‘ื™ืœื•ืช ืœืžืคืชื—ื™ื ื‘ืžื”ืœืš ื”ืจื‘ืขื•ืŸ ื”ืจืืฉื•ืŸ ืฉืœ 2019. ื•ื”ื ืขืฉื• ืืช ื–ื”! ื‘ืกื•ืฃ ื”ืฉื‘ื•ืข ื”ื–ื” ื”ื•ืคื™ืขื• ืงื™ืฉื•ืจื™ื ืœืืจื›ื™ื˜ืงื˜ื•ืจืช/ื’ืจืขื™ื ื™ื ืฉืœ MIPS R6 ื•ืœื›ืœื™ื ื•ืžื•ื“ื•ืœื™ื ืงืฉื•ืจื™ื ื‘ืืชืจ MIPS Open. ื”ื›ืœ ื ื™ืชืŸ ืœื”ื•ืจื™ื“ ื•ืœื”ืฉืชืžืฉ ืœืคื™ ืฉื™ืงื•ืœ ื“ืขืชื›ื ื•ืœื ืชืฆื˜ืจื›ื• ืœืฉืœื ืขื‘ื•ืจื•. ื‘ืขืชื™ื“, ื”ื—ื‘ืจื” ืชืžืฉื™ืš ืœืฉื—ืจืจ ืœืฆื™ื‘ื•ืจ ื’ืจืขื™ื ื™ื ื—ื“ืฉื™ื.

ื”ืžื™ืงืจื•-ืืจื›ื™ื˜ืงื˜ื•ืจื” ื”ืคืชื•ื—ื” ืฉืœ MIPS R6 ืฉื•ื—ืจืจื”

ื—ื‘ื™ืœื•ืช ื”ื”ื•ืจื“ื” ื”ื—ื™ื ืžื™ื•ืช ื”ืจืืฉื•ื ื•ืช ื›ื•ืœืœื•ืช MIPS Instruction Set Architecture (ISA) Release 32 ื”ื•ืจืื•ืช 64 ืกื™ื‘ื™ื•ืช ื•-6 ืกื™ื‘ื™ื•ืช, ื”ืจื—ื‘ื•ืช MIPS SIMD, ื”ืจื—ื‘ื•ืช MIPS DSP, ืชืžื™ื›ืช MIPS Multi-Threading, MIPS MCU, ืงื•ื“ื™ ื“ื—ื™ืกื” microMIPS ื•-MIPS Virtualization. ื›ืžื• ื›ืŸ ื›ืœื•ืœื™ื ื‘-MIPS Open ื”ืืœืžื ื˜ื™ื ื”ื“ืจื•ืฉื™ื ืœืขื™ืฆื•ื‘ ืœื™ื‘ื•ืช MIPS ื‘ืขืฆืžืš - ืืœื• ื”ื MIPS Open Tools ื•-MIPS Open FPGA.

ืืœืžื ื˜ MIPS Open Tools ืžื›ืกื” ืกื‘ื™ื‘ื” ืžืฉื•ืœื‘ืช ืœืคื™ืชื•ื— ืžืขืจื›ื•ืช ืžืฉื•ื‘ืฆื•ืช ืขื‘ื•ืจ ืžืขืจื›ื•ืช ื”ืคืขืœื” ื‘ื–ืžืŸ ืืžืช ื•ืžื•ืฆืจื™ื ืขื‘ื•ืจ ืžืขืจื›ื•ืช ืžืฉื•ื‘ืฆื•ืช ื”ืคื•ืขืœื•ืช ืขืœ ืœื™ื ื•ืงืก. ื–ื” ื™ืืคืฉืจ ืœืžืคืชื— ืœื‘ื ื•ืช, ืœื ืคื•ืช ื‘ืื’ื™ื ื•ืœืคืจื•ืก ืคืจื•ื™ืงื˜ ื‘ื•ื“ื“ ื›ืคืœื˜ืคื•ืจืžืช ื—ื•ืžืจื”-ืชื•ื›ื ื” ืœื”ืคืขืœืช ื™ื™ืฉื•ืžื™ื. ืืœืžื ื˜ MIPS Open FPGA ื”ื•ื ืžื“ืจื™ืš (ืกื‘ื™ื‘ื”) ืœืžื™ ืฉืจื•ืฆื” ืœื”ืขืžื™ืง ืืช ื”ื™ื“ืข ืฉืœื• ื‘ื ื•ืฉื (ืืจื›ื™ื˜ืงื˜ื•ืจื”). MIPS Open FPGA ืชื•ื›ื ืŸ ื‘ืžืงื•ืจ ืขื‘ื•ืจ ืกื˜ื•ื“ื ื˜ื™ื ื•ื ืชืžืš ืขืœ ื™ื“ื™ ื—ื•ืžืจื™ ืขื–ืจ ืžืงื™ืคื™ื ืฉืœ ืžืขื‘ื“ MIPS.

ื”ืžื™ืงืจื•-ืืจื›ื™ื˜ืงื˜ื•ืจื” ื”ืคืชื•ื—ื” ืฉืœ MIPS R6 ืฉื•ื—ืจืจื”

ื›ื‘ื•ื ื•ืก, ื—ื‘ื™ืœืช MIPS Open FPGA ืžื’ื™ืขื” ืขื ืงื•ื“ RTL ืขื‘ื•ืจ ืœื™ื‘ื•ืช MIPS microAptiv ืขืชื™ื“ื™ื•ืช. ืœื™ื‘ื•ืช ืืœื• ื™ื•ื›ืจื–ื• ื‘ื”ืžืฉืš ื”ืฉื ื” ื•ื™ืกื•ืคืงื• ื›ื”ืชื™ื™ื—ืกื•ืช ืœื ืžืกื—ืจื™ืช ืœืžื•ืฆืจื™ื ืขืชื™ื“ื™ื™ื. ืืœื• ื™ื”ื™ื• ืœื™ื‘ื•ืช ืžื—ืฉื•ื‘ ืงื˜ื ื•ืช ื—ืกื›ื•ื ื™ื•ืช ื‘ืื ืจื’ื™ื”, ืฉืฆืคื•ื™ื•ืช ืœืฆืืช ื‘ืขื•ื“ ืžืกืคืจ ืฉื‘ื•ืขื•ืช.




ืžืงื•ืจ: 3dnews.ru

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