Papildus Uplinks Intel C620 sistēmas loģikas arhitektūrā

x86 platform architecture has developed two complementary trends. According to one perspective, integration of computational and control resources within a single chip is essential. The second approach advocates for a division of responsibilities: the processor is equipped with a powerful bus, forming a scalable peripheral ecosystem. This forms the basis of the Intel C620 system logic topology for high-level platforms.

The fundamental difference from the previous Intel C610 chipset lies in the expansion of the communication channel between the processor and peripherals integrated into the PCH chip through the use of PCIe links alongside the traditional DMI bus.

Let's take a closer look at the innovations of the Intel Lewisburg southbridge: what evolutionary and revolutionary approaches have expanded its capabilities in communication with processors?

Evolutionary Changes in CPU-PCH Communication

Within the framework of the evolutionary approach, the main communication channel between the CPU and the southbridge, which is the DMI (Direct Media Interface) bus, has gained support for the PCIe x4 Gen3 mode with a performance of 8.0 GT/S. Previously, in the Intel C610 PCH, communication between the processor and system logic was conducted in PCIe x4 Gen 2 mode at a bandwidth of 5.0 GT/S.

Comparison of the Functionality of Intel C610 and C620 System Logic

Note that this subsystem is significantly more conservative than the built-in PCIe ports of the processor, which are typically used for connecting GPUs and NVMe drives, where PCIe 3.0 has long been applied and the transition to PCI Express Gen4 is planned.

Revolutionary Changes in CPU-PCH Communication

Revolutionary changes include the addition of new PCIe communication channels between the CPU and PCH, referred to as Additional Uplinks. Physically, these are two PCI Express ports operating in PCIe x8 Gen3 and PCIe x16 Gen3 modes, both at 8.0 GT/S.

Three buses are used for the interaction between the CPU and Intel C620 PCH: DMI and two PCI Express ports.

What necessitated a review of the existing communication topology with Intel C620? Firstly, up to four 10GbE network controllers with RDMA functionality can be integrated into the PCH. Secondly, new and faster generation Intel QuickAssist Technology (QAT) coprocessors are responsible for the encryption of network traffic and storage subsystem exchanges, providing hardware support for compression and encryption. Lastly, the "Innovation Engine" — Innovation Engine, kas būs pieejams tikai OEM ražotājiem.

Paplašināmība un elastība

Svarīga īpašība ir iespēja opciju izvēlē ne tikai PCH savienojuma topoloģiju, bet arī mikros ķēdes iekšējo resursu prioritātes piekļuvei ātriem sakaru kanāliem ar centrālo procesoru (procesoriem). Turklāt īpašā EPO (EndPoint Only Mode) režīmā PCH savienojums tiek veikts kā parasta PCI Express ierīce, kurai ir 10 GbE resursi un Intel QAT. Šajā gadījumā klasiskā DMI saskarne, kā arī virkne Legacy sistēmu, kas attēlotas diagrammā melnā krāsā, tiek atslēgtas.

Intel C620 PCH mikroshēmas iekšējā arhitektūra

Teorētiski, tas dod iespēju sistēmā izmantot vairāk nekā vienu Intel C620 PCH mikroshēmu, paplašinot 10 GbE un Intel QAT funkcionalitāti atbilstoši veiktspējas prasībām. Tajā pašā laikā Legacy funkcijas, kas nepieciešamas tikai vienā eksemplārā, var tikt aktivizētas tikai vienai no uzstādītajām PCH mikroshēmām.

Tātad, galīgais lēmums dizainā būs platformas izstrādātājam, kas rīkojas saskaņā ar tehnoloģiskajiem un mārketinga faktoriem atbilstoši katra konkrētā produkta pozicionējumam.

Avots: habr.com