Ko tenei ataata e whakaatu ana: he papa Raspberry Pi3, e hono ana ki a ia ma te hononga GPIO he papa FPGA Mars Rover2rpi (Cyclone IV), e hono ana he aroturuki HDMI. Ko te aroturuki tuarua e hono ana ma te hononga HDMI paerewa o te Raspberry Pi3. Ka mahi tahi nga mea katoa ano he punaha aroturuki rua.
I muri mai ka korero ahau ki a koe me pehea te whakatinanatanga o tenei.
Ko te papa Raspberry Pi3 rongonui he hononga GPIO e taea ai e koe te hono atu i nga kaari roha rereke: nga pūoko, nga rama, nga taraiwa motuka hiko me te maha atu. Ko te mahi tika o ia titi i runga i te hono ka whakawhirinaki ki te whirihoranga tauranga. Ko te whirihoranga GPIO ALT2 ka taea e koe te huri i te hono ki te aratau atanga DPI, Whakaatu Atanga Whakarara. He kaari roha hei hono i nga kaitirotiro VGA ma te DPI. Heoi, ko te tuatahi, kua kore e rite ki te HDMI nga kaitirotiro VGA, tuarua, he pai ake te atanga matihiko i te orite. I tua atu, ko te DAC i runga i enei papa roha VGA ka mahia i roto i te ahua o nga mekameka R-2-R me te nuinga o nga wa kaore e neke atu i te 6 nga moka mo ia tae.
I roto i te aratau ALT2, ko nga titi tūhonohono GPIO te tikanga e whai ake nei:
I konei kua tae ahau ki nga titi RGB o te hononga hono he whero, he kakariki me te kahurangi. Ko etahi atu tohu nui ko nga tohu V-SYNC me H-SYNC, me te CLK. Ko te auau karaka CLK ko te auau e puta ai nga uara pika ki te hono; ka whakawhirinaki ki te aratau ataata kua tohua.
Hei hono i te aroturuki HDMI mamati, me hopu e koe nga tohu DPI o te atanga ka huri ki nga tohu HDMI. Ka taea tenei, hei tauira, ma te whakamahi i etahi momo papa FPGA. I te mea ka puta, he pai te poari Mars Rover2rpi mo enei kaupapa. Ko te mea pono, ko te waahanga matua mo te hono i tenei papa ma te urutau motuhake te ahua penei:
Ka whakamahia tenei papa ki te whakanui ake i te maha o nga tauranga GPIO me te hono atu i etahi atu taputapu peripheral ki te rōpere. I te wa ano, e 4 nga tohu GPIO me tenei hononga e whakamahia ana mo nga tohu JTAG, kia taea ai e te papatono mai i te Raspberry te uta i te firmware FPGA ki te FPGA. Na tenei, kaore tenei hononga paerewa e pai ki ahau; E 4 nga tohu DPI ka heke. Waimarie, ko nga heru taapiri kei runga i te papa he pinout hototahi-Rahipere. Na ka taea e au te huri i te papa 90 nga nekehanga ka hono tonu ki taku rōpere:
Ko te tikanga, me whakamahi koe i tetahi kaiwhakaputa JTAG o waho, engari ehara tenei i te raru.
He raruraru iti tonu. Kaore e taea te whakamahi i nga titi FPGA katoa hei whakaurunga karaka. He iti noa nga titi whakatapua ka taea te whakamahi mo enei kaupapa. Na ka puta mai i konei kaore te tohu GPIO_0 CLK e tae ki te whakaurunga FPGA, ka taea te whakamahi hei whakaurunga karaka FPGA. No reira me tuu tonu e au tetahi waea ki runga i te kameta. Ka hono ahau i te GPIO_0 me te tohu KEY[1] o te poari:
Inaianei ka korero ahau ki a koe mo te kaupapa FPGA. Ko te tino uaua ki te whakaputa tohu HDMI ko nga iarere teitei. Mena ka titiro koe ki te pinout hononga HDMI, ka kite koe ko nga tohu RGB he tohu rereke rangatū inaianei:
Ma te whakamahi i te tohu rerekee ka taea e koe te whawhai i te aratau aratau noa i runga i te raina tuku. I tenei take, ka hurihia te waehere moka-waru taketake o ia tohu tae ki te 10-bit TMDS (Whakawhiti-whakaiti tohu rereke). He tikanga whakawaehere motuhake tenei hei tango i te waahanga DC mai i te tohu me te whakaiti i te whakawhiti tohu i roto i te raina rereke. I te mea ko te paita o te tae me 10 nga moka kia whakawhiti ki runga i te raina rangatū, ka puta ko te auau karaka serializer kia 10 nga wa teitei ake i te auau karaka pika. Ki te tango tatou hei tauira te aratau ataata 1280x720 60Hz, ko te auau pika o tenei aratau ko 74,25 MHz. Me 742,5 MHz te kaiwhakatere.
Ko nga FPGA auau, engari, kaore e taea tenei. Heoi, Waimarie mo matou, kua hangaia e te FPGA nga titi DDIO. He whakatau enei kua oti, penei, 2-ki-1 te raupapa. Arā, ka taea e ratou te whakaputa i nga paraka e rua i runga i te pikinga me te heke o nga tapa o te auau karaka. Ko te tikanga i roto i te kaupapa FPGA ka taea e koe te whakamahi ehara i te 740 MHz, engari ko te 370 MHz, engari me whakamahi koe i nga waahanga whakaputa DDIO i roto i te FPGA. Inaianei ko te 370 MHz kua tino taea te whakatutuki. Kia aroha mai, ko te aratau 1280x720 te rohe. Kaore e taea te whakatutuki i tetahi whakataunga teitei ake i roto i ta maatau FPGA Cyclone IV i whakauruhia ki runga i te poari Mars Rover2rpi.
Na, i roto i te hoahoa, ka haere te auau pika whakauru CLK ki te PLL, ka whakareatia ki te 5. I tenei auau, ka hurihia nga paita R, G, B ki nga takirua moka. Koinei te mahi a te encoder TMDS. Ko te waehere puna i Verilog HDL te ahua penei:
module hdmi(
input wire pixclk, // 74MHz
input wire clk_TMDS2, // 370MHz
input wire hsync,
input wire vsync,
input wire active,
input wire [7:0]red,
input wire [7:0]green,
input wire [7:0]blue,
output wire TMDS_bh,
output wire TMDS_bl,
output wire TMDS_gh,
output wire TMDS_gl,
output wire TMDS_rh,
output wire TMDS_rl
);
wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red ), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_red));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_green));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vsync,hsync}), .VDE(active), .TMDS(TMDS_blue));
reg [2:0] TMDS_mod5=0; // modulus 5 counter
reg [4:0] TMDS_shift_bh=0, TMDS_shift_bl=0;
reg [4:0] TMDS_shift_gh=0, TMDS_shift_gl=0;
reg [4:0] TMDS_shift_rh=0, TMDS_shift_rl=0;
wire [4:0] TMDS_blue_l = {TMDS_blue[9],TMDS_blue[7],TMDS_blue[5],TMDS_blue[3],TMDS_blue[1]};
wire [4:0] TMDS_blue_h = {TMDS_blue[8],TMDS_blue[6],TMDS_blue[4],TMDS_blue[2],TMDS_blue[0]};
wire [4:0] TMDS_green_l = {TMDS_green[9],TMDS_green[7],TMDS_green[5],TMDS_green[3],TMDS_green[1]};
wire [4:0] TMDS_green_h = {TMDS_green[8],TMDS_green[6],TMDS_green[4],TMDS_green[2],TMDS_green[0]};
wire [4:0] TMDS_red_l = {TMDS_red[9],TMDS_red[7],TMDS_red[5],TMDS_red[3],TMDS_red[1]};
wire [4:0] TMDS_red_h = {TMDS_red[8],TMDS_red[6],TMDS_red[4],TMDS_red[2],TMDS_red[0]};
always @(posedge clk_TMDS2)
begin
TMDS_shift_bh <= TMDS_mod5[2] ? TMDS_blue_h : TMDS_shift_bh [4:1];
TMDS_shift_bl <= TMDS_mod5[2] ? TMDS_blue_l : TMDS_shift_bl [4:1];
TMDS_shift_gh <= TMDS_mod5[2] ? TMDS_green_h : TMDS_shift_gh [4:1];
TMDS_shift_gl <= TMDS_mod5[2] ? TMDS_green_l : TMDS_shift_gl [4:1];
TMDS_shift_rh <= TMDS_mod5[2] ? TMDS_red_h : TMDS_shift_rh [4:1];
TMDS_shift_rl <= TMDS_mod5[2] ? TMDS_red_l : TMDS_shift_rl [4:1];
TMDS_mod5 <= (TMDS_mod5[2]) ? 3'd0 : TMDS_mod5+3'd1;
end
assign TMDS_bh = TMDS_shift_bh[0];
assign TMDS_bl = TMDS_shift_bl[0];
assign TMDS_gh = TMDS_shift_gh[0];
assign TMDS_gl = TMDS_shift_gl[0];
assign TMDS_rh = TMDS_shift_rh[0];
assign TMDS_rl = TMDS_shift_rl[0];
endmodule
module TMDS_encoder(
input clk,
input [7:0] VD, // video data (red, green or blue)
input [1:0] CD, // control data
input VDE, // video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)
output reg [9:0] TMDS = 0
);
wire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];
wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);
wire [8:0] q_m = {~XNOR, q_m[6:0] ^ VD[7:1] ^ {7{XNOR}}, VD[0]};
reg [3:0] balance_acc = 0;
wire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4'd4;
wire balance_sign_eq = (balance[3] == balance_acc[3]);
wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;
wire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));
wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;
wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};
wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);
always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;
always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;
endmodule
Katahi ka whangaia nga takirua whakaputa ki te putanga DDIO, ka puta he tohu moka-tahi i runga i nga tapa piki me te heke.
Ko te DDIO ano ka taea te korero me te waehere Verilog e whai ake nei:
module ddio(
input wire d0,
input wire d1,
input wire clk,
output wire out
);
reg r_d0;
reg r_d1;
always @(posedge clk)
begin
r_d0 <= d0;
r_d1 <= d1;
end
assign out = clk ? r_d0 : r_d1;
endmoduleEngari kaore pea e mahi pera. Me whakamahi koe i te megafunction a Alter ALTDIO_OUT kia taea ai nga huānga whakaputa DDIO. Ka whakamahia e taku kaupapa te waahanga whare pukapuka ALTDIO_OUT.
He ahua uaua tenei katoa, engari he pai.
Ka taea e koe te tiro i nga waehere puna katoa kua tuhia ki Verilog HDL .
Ko te miihini whakahiato mo te FPGA ka whiti ki roto i te maramara EPCS i whakauruhia ki runga i te papa Mars Rover2rpi. No reira, ka tukuna te mana ki te poari FPGA, ka arawhiti te FPGA mai i te mahara kohiko ka timata.
Inaianei me korero tatou mo te whirihoranga o te Raspberry ano.
Kei te mahi au i nga whakamatautau mo te Raspberry PI OS (32 bit) i runga i te Debian Buster, Putanga: Akuhata 2020,
Te ra tuku:2020-08-20, Putanga Kernel:5.4.
Me mahi koe e rua nga mea:
- whakatika i te kōnae config.txt;
- hanga he whirihoranga tūmau X hei mahi me nga kaitirotiro e rua.
Ina whakatika i te kōnae /boot/config.txt ka hiahia koe:
- whakakorehia te whakamahinga o i2c, i2s, spi;
- whakaahei te aratau DPI ma te whakakikorua dtoverlay=dpi24;
- whirihora aratau ataata 1280×720 60Hz, 24 bits ia pika i runga i te DPI;
- whakapūtāhia te maha o nga framebuffers 2 (max_framebuffers=2, katahi ka puta te taputapu tuarua /dev/fb1)
He penei te ahua o te tuhinga katoa o te konae config.txt.
# For more options and information see
# http://rpf.io/configtxt
# Some settings may impact device functionality. See link above for details
# uncomment if you get no picture on HDMI for a default "safe" mode
#hdmi_safe=1
# uncomment this if your display has a black border of unused pixels visible
# and your display can output without overscan
disable_overscan=1
# uncomment the following to adjust overscan. Use positive numbers if console
# goes off screen, and negative if there is too much border
#overscan_left=16
#overscan_right=16
#overscan_top=16
#overscan_bottom=16
# uncomment to force a console size. By default it will be display's size minus
# overscan.
#framebuffer_width=1280
#framebuffer_height=720
# uncomment if hdmi display is not detected and composite is being output
hdmi_force_hotplug=1
# uncomment to force a specific HDMI mode (this will force VGA)
#hdmi_group=1
#hdmi_mode=1
# uncomment to force a HDMI mode rather than DVI. This can make audio work in
# DMT (computer monitor) modes
#hdmi_drive=2
# uncomment to increase signal to HDMI, if you have interference, blanking, or
# no display
#config_hdmi_boost=4
# uncomment for composite PAL
#sdtv_mode=2
#uncomment to overclock the arm. 700 MHz is the default.
#arm_freq=800
# Uncomment some or all of these to enable the optional hardware interfaces
#dtparam=i2c_arm=on
#dtparam=i2s=on
#dtparam=spi=on
dtparam=i2c_arm=off
dtparam=spi=off
dtparam=i2s=off
dtoverlay=dpi24
overscan_left=0
overscan_right=0
overscan_top=0
overscan_bottom=0
framebuffer_width=1280
framebuffer_height=720
display_default_lcd=0
enable_dpi_lcd=1
dpi_group=2
dpi_mode=87
#dpi_group=1
#dpi_mode=4
dpi_output_format=0x6f027
dpi_timings=1280 1 110 40 220 720 1 5 5 20 0 0 0 60 0 74000000 3
# Uncomment this to enable infrared communication.
#dtoverlay=gpio-ir,gpio_pin=17
#dtoverlay=gpio-ir-tx,gpio_pin=18
# Additional overlays and parameters are documented /boot/overlays/README
# Enable audio (loads snd_bcm2835)
dtparam=audio=on
[pi4]
# Enable DRM VC4 V3D driver on top of the dispmanx display stack
#dtoverlay=vc4-fkms-v3d
max_framebuffers=2
[all]
#dtoverlay=vc4-fkms-v3d
max_framebuffers=2
I muri i tenei, me hanga e koe he konae whirihoranga mo te tūmau X ki te whakamahi i nga kaitirotiro e rua i runga i nga framebuffers e rua /dev/fb0 me /dev/fb1:
He penei taku konae whirihora /usr/share/x11/xorg.conf.d/60-dualscreen.conf
Section "Device"
Identifier "LCD"
Driver "fbturbo"
Option "fbdev" "/dev/fb0"
Option "ShadowFB" "off"
Option "SwapbuffersWait" "true"
EndSection
Section "Device"
Identifier "HDMI"
Driver "fbturbo"
Option "fbdev" "/dev/fb1"
Option "ShadowFB" "off"
Option "SwapbuffersWait" "true"
EndSection
Section "Monitor"
Identifier "LCD-monitor"
Option "Primary" "true"
EndSection
Section "Monitor"
Identifier "HDMI-monitor"
Option "RightOf" "LCD-monitor"
EndSection
Section "Screen"
Identifier "screen0"
Device "LCD"
Monitor "LCD-monitor"
EndSection
Section "Screen"
Identifier "screen1"
Device "HDMI"
Monitor "HDMI-monitor"
EndSection
Section "ServerLayout"
Identifier "default"
Option "Xinerama" "on"
Option "Clone" "off"
Screen 0 "screen0"
Screen 1 "screen1" RightOf "screen0"
EndSection
Ana, mena kaore ano kia whakauruhia, na me whakauru koe ki te Xinerama. Na ka tino whakawhānuihia te waahi papamahi ki nga kaitirotiro e rua, penei i te whakaaturanga ataata i runga ake nei.
Heoi ano pea. Na, ka taea e nga rangatira o te Raspberry Pi3 te whakamahi i nga kaitirotiro e rua.
Ka kitea te whakaahuatanga me te hoahoa ara iahiko o te poari Mars Rover2rpi .
Source: will.com