{"id":33621,"date":"2019-10-31T21:53:47","date_gmt":"2019-10-31T18:53:47","guid":{"rendered":"https:\/\/prohoster.info\/blog\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620\/"},"modified":"2019-10-31T21:53:47","modified_gmt":"2019-10-31T18:53:47","slug":"additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","status":"publish","type":"post","link":"https:\/\/prohoster.info\/no\/blog\/administrirovanie\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","title":{"rendered":"Ytterligere uplinks i systemlogikkens arkitektur for Intel C620","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

I arkitekturen til x86-plattformer har det oppst\u00e5tt to retninger som komplementerer hverandre. If\u00f8lge en versjon b\u00f8r man bevege seg mot integrasjon av beregnings- og styringsressurser i en enkelt brikke. Den andre tiln\u00e6rmingen f\u00f8lger en fordeling av oppgaver: prosessoren utstyres med en kraftig buss som danner et perifert, skalerbart \u00f8kosystem. Dette ligger til grunn for topologien i Intel C620-systemlogikken for h\u00f8ytytende plattformer.<\/a><\/noindex><\/p>\n

Det prinsipielle skillet fra den forrige Intel C610-brikken ligger i utvidelsen av kommunikasjonskanalen mellom prosessoren og periferiutstyret, som inng\u00e5r i PCH-brikken, ved \u00e5 bruke PCIe-lenker i tillegg til den tradisjonelle DMI-bussen.<\/p>\n

\"Ytterligere
\n
\nLa oss se n\u00e6rmere p\u00e5 nyhetene i Intel Lewisburg-sydbrikken: hvilke evolusjon\u00e6re og revolusjon\u00e6re tiln\u00e6rminger har utvidet dens fullmakter i kommunikasjon med prosessorene?<\/p>\n

Evolusjon\u00e6re endringer i CPU-PCH kommunikasjon<\/h2>\n

\nInnom den evolusjon\u00e6re tiln\u00e6rmingen har hovedkommunikasjonskanalen mellom CPU og sydbrikken, som er DMI-bussen (Direct Media Interface), f\u00e5tt st\u00f8tte for PCIe x4 Gen3-modus med en ytelse p\u00e5 8.0 GT\/S. Tidligere, i Intel C610 PCH, ble kommunikasjonen mellom prosessoren og systemlogikken utf\u00f8rt i PCIe x4 Gen 2-modus med en b\u00e5ndbredde p\u00e5 5.0 GT\/S.<\/p>\n

\"Ytterligere
\n
\nSammenligning av funksjonaliteten til systemlogikken Intel C610 og C620<\/em><\/p>\n

Vi merker oss at dette subsystemet er betydelig mer konservativt enn de innebygde PCIe-portene i prosessoren, som vanligvis brukes for tilkobling av GPU-er og NVMe-lagringsenheter, hvor PCIe 3.0 lenge har blitt brukt, og overgangen til PCI Express Gen4 er p\u00e5 trappene.<\/p>\n

Revolusjon\u00e6re endringer i CPU-PCH kommunikasjon<\/h2>\n

\nRevolusjon\u00e6re endringer inkluderer tillegget av nye PCIe-kanaler for kommunikasjon mellom CPU og PCH, kalt Additional Uplinks. Fysisk best\u00e5r dette av to PCI Express-porter som opererer i PCIe x8 Gen3 og PCIe x16 Gen3-modus, begge ved 8.0 GT\/S.<\/p>\n

\"Ytterligere
\n
\nFor interaksjonen mellom CPU og Intel C620 PCH brukes 3 busser: DMI og to PCI Express-porter.<\/em><\/p>\n

Hva krevde en gjennomgang av den eksisterende kommunikasjonstopologien med Intel C620? For det f\u00f8rste kan PCH integrere opptil 4 nettverkskontrollere av typen 10GbE med RDMA-funksjonalitet. For det andre er det nye og raskere generasjonen av Intel QuickAssist Technology (QAT)-ko prosessorer ansvarlig for kryptering av nettverkstrafikk og kommunikasjon med lagringssystemet, og de tilbyr maskinvarest\u00f8tte for komprimering og kryptering. Og til slutt \u2014 \"innovasjonsmotoren\" \u2014 Innovation Engine<\/a><\/noindex>, som kun vil v\u00e6re tilgjengelig for OEM-produsenter.<\/p>\n

Skalerbarhet og fleksibilitet<\/h2>\n

\nEn viktig egenskap er muligheten for valgfritt valg av ikke bare topologien til PCH-tilkoblingen, men ogs\u00e5 prioriteringene for de interne ressursene til brikken i tilgangen til h\u00f8yhastighets kommunikasjon med prosessoren(e). I tillegg, i den spesielle tilstanden EPO (EndPoint Only Mode), kobles PCH til som en vanlig PCI Express-enhet som inneholder ressursene 10 GbE og Intel QAT. Samtidig er den klassiske DMI-grensesnittet, samt en rekke Legacy-undersystemer, vist i svart p\u00e5 diagrammet, koblet fra.<\/p>\n

\"Ytterligere
\n
\nDen interne arkitekturen til Intel C620 PCH-brikken<\/em><\/p>\n

Teoretisk gj\u00f8r dette det mulig \u00e5 bruke mer enn \u00e9n Intel C620 PCH-brikke i systemet, og dermed skalere funksjonaliteten til 10 GbE og Intel QAT i henhold til ytelseskravene. Samtidig kan Legacy-funksjoner, som bare trengs i en enkelt kopi, kun aktiveres p\u00e5 \u00e9n av de installerte PCH-brikkene.<\/p>\n

Dermed vil den endelige beslutningen i designet ligge hos plattformutvikleren, basert p\u00e5 b\u00e5de teknologiske og markedsf\u00f8ringsfaktorer i henhold til posisjoneringen av hvert enkelt produkt.
\n
Kilde: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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