Pulojekiti ya Vortex 3.0, yomwe imapanga GPGPU yotseguka kutengera kapangidwe ka malangizo a RISC-V ndipo idapangidwira makompyuta ofanana pogwiritsa ntchito OpenCL API ndi chitsanzo cha SIMT (Single Instruction, Multiple Threads), tsopano ikupezeka. Pulojekitiyi ingagwiritsidwenso ntchito pakufufuza zithunzi za 3D komanso kupanga mapangidwe atsopano a GPU. Ma schematics, mafotokozedwe a hardware block mu Verilog, simulator, ma driver, ndi zolemba za kapangidwe zomwe zikugwirizana nazo zimagawidwa pansi pa layisensi ya Apache 2.0.
GPGPU imachokera pa RISC-V ISA yokhazikika, yowonjezeredwa ndi malangizo owonjezera othandizira mawonekedwe a GPU ndi kasamalidwe ka ulusi. Kusintha kwa kapangidwe ka malangizo a RISC-V kumasungidwa pang'ono, ndipo malangizo omwe alipo a vector amagwiritsidwa ntchito nthawi iliyonse yomwe ingatheke. Malangizo owonjezera akuphatikizapo: "tex" yofulumizitsa kukonza kapangidwe; vx_rast yowongolera rasterization; vx_rop yokonza zidutswa, kuya, ndi kuwonekera bwino; vx_imadd yogwirira ntchito zochulukitsa ndi kuwonjezera; vx_wspawn, vx_split, vx_join, vx_tmc, ndi vx_bar yoyambitsa magulu a ulusi (ma wavefront) omwe amachitidwa motsatizana ndi SIMD Engine.
GPGPU yomwe ikupangidwa imathandizira mapangidwe a malangizo a RISC-V RV32IMF ndi RV64IMAFD a 32- ndi 64-bit ndipo ikhoza kuphatikiza kukumbukira komwe kungasinthidwe, ma cache a L1, L2, ndi L3, ndi chiwerengero chosinthika cha ma cores, ma warp, ndi ma thread. Pakati pa chilichonse pakhozanso kuphatikiza chiwerengero chosinthika cha ma ALU, ma FPU, ma LSU, ndi ma SFU. Ma Xilinx ndi ma Altera FPGA angagwiritsidwe ntchito popanga ma prototyping, ndipo Verilator (Verilog simulator), RTLSIM (RTL simulation), ndi SimX (software simulation) angagwiritsidwe ntchito popanga ma chip simulation.
Pakupanga mapulogalamu, pali chida chogwiritsira ntchito, kuphatikizapo mitundu ya PoCL (OpenCL compiler ndi runtime), LLVM/Clang, GCC, ndi Binutils yosinthidwa ndi Vortex. Pulojekitiyi imathandizira mawonekedwe a OpenCL 1.2 ndipo imagwiritsa ntchito chithandizo cha SPIR-V pakati pa mithunzi kudzera mu kumasulira ku OpenCL.
Zosintha mu Vortex 3.0 zikuphatikizapo:
- Chosungira zithunzi cha hardware chawonjezedwa, kuphatikizapo mabuloko a rasterization, texture mapping, ndi output merging (OM). Choyendetsa cha Vulkan, vortexpipe, chapangidwa ku Mesa kutengera chosungira zithunzi chomwe chagwiritsidwa ntchito komanso rasterizer ya lavapipe software.
- Mphamvu za Tensor Core, zomwe zapangidwa kuti zifulumizitse kugwiritsa ntchito mitundu yophunzirira makina, zakulitsidwa, zikuthandizira sparsity yokonzedwa bwino yochepetsera matrices olemera.
- Ntchito ya WGMMA (warpgroup-level matrix multiplication) yagwiritsidwa ntchito pochulukitsa matrix mu asynchronous mode.
- Yawonjezera injini ya DXA (Data Transfer Acceleration) kuti ifulumizitse kusamutsa deta kuchokera ku global kupita ku local memory.
- Kapangidwe katsopano kakhazikitsidwa pogwiritsa ntchito purosesa yolamula (CP) ndi hardware scheduler ya computing cores (KMU - Kernel Management Unit), yomwe imalola kutumiza ulusi wa computing kumbali ya chip.
- Laibulale yatsopano ya nthawi yogwirira ntchito ikuperekedwa yomwe imagwira ntchito mosaletsa ndipo imapereka zotsalira zomwe zimamasulira kukhala malamulo a hardware omwe amachitidwa mosasinthasintha. Mizere, zochitika, ma module, ndi kulunzanitsa kutengera zopinga zosasinthasintha ndi mawu oti arrive/wait/event amathandizidwa.
- Thandizo la RISC-V Shortened Instructions (RVC) lawonjezeredwa.
- Chithandizo cha zida zamagetsi pa ntchito za atomiki (Hardware Atomics) chakhazikitsidwa.
- FPU yasinthidwa kwathunthu ndipo ma block atsopano ochulukitsa (Wallace-tree, Folded-radix) ndi adder (Kogge-Stone) ayambitsidwa.
- Yawonjezera purosesa ya memory yochokera ku chipangizo choyang'anira kukumbukira (MMU) chothandizidwa ndi kapangidwe ka ma adilesi a 32-bit SV32.
- Chithandizo cha kukulitsa kwa RISC-V Zicond pogwiritsa ntchito njira zodziyimira pawokha.
- Kutseka kwa wotchi kogwirizana.
- Chithandizo cha chilankhulo cha HIP (Heterogeneous Interface for Portability) chakhazikitsidwa kudzera mu chipStar framework, yomwe imamasulira HIP kukhala SPIR-V.
- Kuphatikiza kwathunthu ndi simulator ya GEM5 kwaperekedwa, ndipo chithandizo cha simulator ya SimX pa kapangidwe ka TLM (Transaction-Level Modeling) chawonjezedwa.
- Thandizo la Synopsys ndi Yosys toolkits la logic synthesis for manufacturing chips, komanso kuthandizira kugwiritsa ntchito ASAP7 (7nm), SAED14 (14nm), ndi NanGate (15nm) standard element libraries.
- Chida chothandizira chasinthidwa kukhala LLVM 20 ndi POCL 7.0.
Source: opennet.ru
