{"id":103469,"date":"2022-03-03T15:36:38","date_gmt":"2022-03-03T13:36:39","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/intel-amd-i-arm-predstavili-ucie-otkrytyj-standart-dlya-chipletov"},"modified":"2022-03-03T15:36:38","modified_gmt":"2022-03-03T13:36:39","slug":"intel-amd-i-arm-predstavili-ucie-otkrytyj-standart-dlya-chipletov","status":"publish","type":"post","link":"https:\/\/prohoster.info\/pl\/blog\/news\/intel-amd-i-arm-predstavili-ucie-otkrytyj-standart-dlya-chipletov","title":{"rendered":"Intel, AMD i ARM zaprezentowali UCIe, otwarty standard dla chiplet\u00f3w","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Og\u0142oszono utworzenie konsorcjum UCIe (Universal Chiplet Interconnect Express), kt\u00f3rego celem jest rozw\u00f3j otwartych specyfikacji i stworzenie ekosystemu dla technologii chiplet\u00f3w. Chiplety umo\u017cliwiaj\u0105 tworzenie hybrydowych uk\u0142ad\u00f3w scalonych (modu\u0142\u00f3w wielochipowych) z niezale\u017cnych blok\u00f3w p\u00f3\u0142przewodnikowych, kt\u00f3re nie s\u0105 powi\u0105zane z jednym producentem i komunikuj\u0105 si\u0119 ze sob\u0105 za pomoc\u0105 standardowego, szybkiego interfejsu UCIe.

\"Intel,<\/center> <\/p>\n

Do opracowania specjalizowanego rozwi\u0105zania, na przyk\u0142ad stworzenia procesora z wbudowanym akceleratorem do uczenia maszynowego lub przetwarzania operacji sieciowych, wystarczy wykorzysta\u0107 ju\u017c istniej\u0105ce chiplety z rdzeniami procesor\u00f3w lub akceleratorami oferowanymi przez r\u00f3\u017cnych producent\u00f3w. Je\u015bli brak jest standardowych rozwi\u0105za\u0144, mo\u017cna stworzy\u0107 w\u0142asny chiplet z wymagan\u0105 funkcjonalno\u015bci\u0105, wykorzystuj\u0105c preferowane technologie i rozwi\u0105zania. <\/p>\n

Po tym wystarczy po\u0142\u0105czy\u0107 wybrane chiplety, korzystaj\u0105c z modu\u0142owej konstrukcji w stylu LEGO (proponowana technologia przypomina u\u017cycie kart PCIe do sk\u0142adania wn\u0119trza komputera, ale na poziomie uk\u0142ad\u00f3w scalonych). Wymiana danych i interakcja mi\u0119dzy chipletami odbywa si\u0119 za pomoc\u0105 wysokowydajnego interfejsu UCIe, a do kompozycji blok\u00f3w stosuje si\u0119 paradygmat \u201esystemu w opakowaniu\u201d (SoP, system-on-package) zamiast \u201esystemu na chipie\u201d (SoC, system-on-chip). <\/p>\n

W por\u00f3wnaniu do SoC technologia chiplet\u00f3w pozwala na tworzenie wymiennych i wielokrotnego u\u017cytku blok\u00f3w p\u00f3\u0142przewodnikowych, kt\u00f3re mo\u017cna stosowa\u0107 w r\u00f3\u017cnych urz\u0105dzeniach, co znacznie obni\u017ca koszty opracowania chip\u00f3w. W systemach opartych na chipletach mo\u017cna \u0142\u0105czy\u0107 r\u00f3\u017cne architektury i procesy produkcyjne \u2014 poniewa\u017c ka\u017cdy chiplet dzia\u0142a niezale\u017cnie, komunikuj\u0105c si\u0119 za po\u015brednictwem standardowych interfejs\u00f3w, w jednym produkcie mog\u0105 by\u0107 \u0142\u0105czone bloki z r\u00f3\u017cnymi architekturami zestawu instrukcji (ISA), takimi jak RISC-V, ARM i x86. Zastosowanie chiplet\u00f3w upraszcza r\u00f3wnie\u017c testowanie \u2014 ka\u017cdy chiplet mo\u017ce by\u0107 testowany osobno na etapie przed integracj\u0105 w gotowym rozwi\u0105zaniu.

\"Intel,<\/center> <\/p>\n

Do inicjatywy promuj\u0105cej technologi\u0119 chiplet\u00f3w do\u0142\u0105czy\u0142y firmy Intel, AMD, ARM, Qualcomm, Samsung, ASE (Advanced Semiconductor Engineering), Google Cloud, Meta\/Facebook, Microsoft oraz Taiwan Semiconductor Manufacturing Company. Publiczno\u015bci przedstawiono otwarty standard UCIe 1.0, kt\u00f3ry standaryzuje metody \u0142\u0105czenia uk\u0142ad\u00f3w scalonych na wsp\u00f3lnej bazie, stos protoko\u0142\u00f3w, model programowy oraz proces testowania. Z interfejs\u00f3w do \u0142\u0105czenia chiplet\u00f3w og\u0142oszono wsparcie dla PCIe (PCI Express) oraz CXL (Compute Express Link).
\n
\u0179r\u00f3d\u0142o: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041e\u0431\u044a\u044f\u0432\u043b\u0435\u043d\u043e \u043e \u0444\u043e\u0440\u043c\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0438 \u043a\u043e\u043d\u0441\u043e\u0440\u0446\u0438\u0443\u043c\u0430 UCIe (Universal Chiplet Interconnect Express), \u043d\u0430\u0446\u0435\u043b\u0435\u043d\u043d\u043e\u0433\u043e \u043d\u0430 \u0440\u0430\u0437\u0432\u0438\u0442\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0445 \u0441\u043f\u0435\u0446\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u0439 \u0438 \u0444\u043e\u0440\u043c\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u044d\u043a\u043e\u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0434\u043b\u044f \u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0438 \u0447\u0438\u043f\u043b\u0435\u0442\u043e\u0432 (chiplet). \u0427\u0438\u043f\u043b\u0435\u0442\u044b \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u044e\u0442 \u0441\u043e\u0437\u0434\u0430\u0432\u0430\u0442\u044c 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[…]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103470,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103469","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Intel, AMD i ARM zaprezentowali UCIe, otwarty standard dla chiplet\u00f3w | ProHoster","description":"Og\u0142oszono o powstaniu konsorcjum UCIe (Universal Chiplet Interconnect Express), kt\u00f3rego celem jest rozw\u00f3j otwartych specyfikacji oraz stworzenie ekosystemu dla technologii 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