{"id":116366,"date":"2024-06-05T15:40:14","date_gmt":"2024-06-05T13:40:14","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/nabor-patchej-dlya-uskoreniya-shifrovaniya-deshifrovaniya-aes-gcm"},"modified":"2024-06-05T15:40:14","modified_gmt":"2024-06-05T13:40:14","slug":"nabor-patchej-dlya-uskoreniya-shifrovaniya-deshifrovaniya-aes-gcm","status":"publish","type":"post","link":"https:\/\/prohoster.info\/pl\/blog\/news\/nabor-patchej-dlya-uskoreniya-shifrovaniya-deshifrovaniya-aes-gcm","title":{"rendered":"Zestaw poprawek do przyspieszenia szyfrowania\/dekodowania AES-GCM","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\"Zestaw <\/p>\n

2 czerwca Eric Biggers (in\u017cynier z Google) przedstawi\u0142 nowe implementacje AES-XTS dla znacznie wy\u017cszej wydajno\u015bci procesor\u00f3w Intel\/AMD z u\u017cyciem nowych zestaw\u00f3w kod\u00f3w AES-NI + AVX, VAES + AVX2, VAES + AVX10\/256 oraz VAES + AVX10\/512.<\/p>\n

Kod AES-NI GCM zast\u0119puje poprzedni, napisany przez Intel, i eliminuje istniej\u0105ce zidentyfikowane problemy:<\/p>\n

\n

\u201eTen zestaw aktualizacji wprowadza implementacj\u0119 AES-GCM (tryb Galois\/Counter) w VAES i AVX512\/AVX10, co zwi\u0119ksza wydajno\u015b\u0107 AES-GCM o 162%. Dodatkowo, zast\u0119puje on starszy kod AES-NI GCM od Intela nowym kodem, kt\u00f3ry jest nieco szybszy i naprawia szereg problem\u00f3w, w tym ogromny rozmiar pliku binarnego, przekraczaj\u0105cy 250 KB. Szczeg\u00f3\u0142y znajdziesz w poprawkach.<\/p>\n<\/blockquote>\n

\n

Ostatecznym stanem kodu assemblera x86_64 AES-GCM jest to, \u017ce otrzymujemy dwa pliki assemblerowe: jeden generuje kod AES-NI z AVX lub bez niego, a drugi generuje kod VAES z AVX512\/AVX10 z wektorami 256-bitowymi lub 512-bitowymi. Brakuje mu wsparcia dla pojedynczego VAES (bez AVX512\/AVX10). To nieco r\u00f3\u017cni si\u0119 od tego, co zrobi\u0142em z AES-XTS, gdzie jeden plik generuje kod AVX i AVX512\/AVX10, w tym kod z wykorzystaniem tylko VAES (bez AVX512\/AVX10), a inny plik generuje tylko kod, inny ni\u017c AVX. Jednak w tej chwili wydaje si\u0119 to w\u0142a\u015bciwym wyborem dla ka\u017cdego konkretnego algorytmu, bior\u0105c pod uwag\u0119, \u017ce ograniczenie do 16 rejestr\u00f3w SIMD i 128-bitowych wektor\u00f3w doprowadzi\u0142o do znacznie r\u00f3\u017cni\u0105cych si\u0119 rozwi\u0105za\u0144 konstrukcyjnych w AES-GCM, ale nie na tyle w AES-XTS. Procesory dostarczane wy\u0142\u0105cznie z VAES r\u00f3wnie\u017c wydaj\u0105 si\u0119 zjawiskiem przej\u015bciowym, wi\u0119c by\u0107 mo\u017ce nie powinni\u015bmy zbytnio stara\u0107 si\u0119 wspiera\u0107 t\u0119 kombinacj\u0119.\u201d<\/p>\n<\/blockquote>\n

\u0179r\u00f3d\u0142o: linux.org.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

2 \u0438\u044e\u043d\u044f \u042d\u0440\u0438\u043a \u0411\u0438\u0433\u0433\u0435\u0440\u0441 (\u0438\u043d\u0436\u0435\u043d\u0435\u0440 \u0438\u0437 Google) \u043f\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u0438\u043b \u043d\u043e\u0432\u044b\u0435 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 AES-XTS \u0434\u043b\u044f \u0433\u043e\u0440\u0430\u0437\u0434\u043e \u0431\u043e\u043b\u0435\u0435 \u0432\u044b\u0441\u043e\u043a\u043e\u0439 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Intel\/AMD \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e \u043d\u043e\u0432\u044b\u0445 \u043d\u0430\u0431\u043e\u0440\u043e\u0432 \u043a\u043e\u0434\u0430 AES-NI + AVX, VAES + AVX2, VAES + AVX10\/256 \u0438 VAES + AVX10\/512. \u041a\u043e\u0434 AES-NI GCM \u0437\u0430\u043c\u0435\u043d\u044f\u0435\u0442 \u0441\u043e\u0431\u043e\u0439 \u043f\u0440\u0435\u0434\u044b\u0434\u0443\u0449\u0438\u0439, \u043d\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0439 Intel, \u0438 \u0443\u0441\u0442\u0440\u0430\u043d\u044f\u0435\u0442 \u0441\u0443\u0449\u0435\u0441\u0442\u0432\u0443\u044e\u0449\u0438\u0435 \u0432\u044b\u044f\u0432\u043b\u0435\u043d\u043d\u044b\u0435 \u043f\u0440\u043e\u0431\u043b\u0435\u043c\u044b: «\u042d\u0442\u043e\u0442 \u043d\u0430\u0431\u043e\u0440 \u043e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u0439 \u0434\u043e\u0431\u0430\u0432\u043b\u044f\u0435\u0442 \u0432 VAES […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":116367,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-116366","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Zestaw poprawek do przyspieszenia szyfrowania\/dekodowania AES-GCM | ProHoster","description":"2 czerwca Eric Biggers (in\u017cynier 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