![\"ASIC](\"\/wp-content\/uploads\/2019\/03\/cdc1ca695edfab035c28a2488102d985.jpg\")
<\/p>\nMa\u0142o kto b\u0119dzie si\u0119 spiera\u0142 z tym, \u017ce projektowanie niestandardowych uk\u0142ad\u00f3w scalonych (ASIC) to proces daleki od bycia prostym i szybkim. Chcia\u0142oby si\u0119, aby by\u0142o szybciej: dzisiaj wydano algorytm, a za tydzie\u0144 odebrano gotowy projekt cyfrowy. Chodzi o to, \u017ce wysoce wyspecjalizowane ASIC to niemal\u017ce produkt na miar\u0119. Takie rzadko s\u0105 potrzebne w milionowych partiach, na kt\u00f3re mo\u017cna by wyda\u0107 nieograniczone \u015brodki finansowe i zasoby ludzkie, je\u015bli trzeba to wykona\u0107 w jak najkr\u00f3tszym czasie. Specjalizowane, a zatem najbardziej efektywne dla rozwi\u0105zywania swoich zada\u0144 ASIC powinny by\u0107 ta\u0144sze w opracowaniu, co staje si\u0119 niezwykle istotne na obecnym etapie rozwoju uczenia maszynowego. Na tym polu nie wystarczy bagaz zdobyty przez rynek komputerowy i zw\u0142aszcza prze\u0142omy GPU w kierunku uczenia maszynowego (ML).<\/p>\n
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Aby przyspieszy\u0107 projektowanie ASIC do zada\u0144 ML, agencja DARPA uruchamia nowy program - Real Time Machine Learning (RTML). Program uczenia maszynowego w czasie rzeczywistym zak\u0142ada opracowanie kompilatora lub platformy programowej, kt\u00f3ra mog\u0142aby automatycznie projektowa\u0107 architektur\u0119 chipu dla konkretnego frameworka ML. Platforma ma automatycznie analizowa\u0107 proponowany algorytm uczenia maszynowego oraz zestaw danych do nauki tego algorytmu, po czym w j\u0119zyku Verilog powinna wyda\u0107 kod do stworzenia wyspecjalizowanego ASIC. Specjali\u015bci ds. rozwoju algorytm\u00f3w ML nie posiadaj\u0105 wiedzy projektant\u00f3w chip\u00f3w, a projektanci rzadko znaj\u0105 zasady uczenia maszynowego. Program RTML ma na celu po\u0142\u0105czenie zalet jednych i drugich w zautomatyzowanej platformie do opracowywania ASIC dla uczenia maszynowego.<\/p>\n
W trakcie cyklu \u017cycia programu RTML znalezione rozwi\u0105zania b\u0119d\u0105 musia\u0142y by\u0107 testowane w dw\u00f3ch g\u0142\u00f3wnych obszarach zastosowania: dzia\u0142aniu w sieciach 5G oraz przetwarzaniu obraz\u00f3w. Program RTML oraz stworzone platformy programowe do automatycznego projektowania akcelerator\u00f3w ML b\u0119d\u0105 wykorzystywane do opracowywania i testowania nowych algorytm\u00f3w ML oraz zestaw\u00f3w danych. Dzi\u0119ki temu, jeszcze przed projektowaniem «krzemu», b\u0119dzie mo\u017cliwe ocenienie potencja\u0142u nowych framework\u00f3w. Partnerem DARPA w programie RTML b\u0119dzie Narodowa Fundacja Nauki (NSF), kt\u00f3ra r\u00f3wnie\u017c zajmuje si\u0119 problemami uczenia maszynowego i rozwojem algorytm\u00f3w ML. Opracowany kompilator zostanie przekazany NSF, a DARPA spodziewa si\u0119 otrzyma\u0107 z powrotem kompilator i platform\u0119 do projektowania algorytm\u00f3w ML. W przysz\u0142o\u015bci projektowanie sprz\u0119tu oraz tworzenie algorytm\u00f3w b\u0119d\u0105 kompleksowym rozwi\u0105zaniem, co doprowadzi do powstania samo ucz\u0105cych si\u0119 w czasie rzeczywistym system\u00f3w maszynowych.<\/p>\n
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