{"id":54142,"date":"2019-12-19T00:00:00","date_gmt":"2019-12-18T21:00:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/blog_prohoster\/utechka-podtverzhdaet-uvelichenie-kesha-vtorogo-urovnya-u-budushhih-protsessorov-intel"},"modified":"2020-02-18T14:02:07","modified_gmt":"2020-02-18T11:02:07","slug":"utechka-podtverzhdaet-uvelichenie-kesha-vtorogo-urovnya-u-budushhih-protsessorov-intel","status":"publish","type":"post","link":"https:\/\/prohoster.info\/pl\/blog\/news\/utechka-podtverzhdaet-uvelichenie-kesha-vtorogo-urovnya-u-budushhih-protsessorov-intel","title":{"rendered":"Wycieki potwierdzaj\u0105 zwi\u0119kszenie pami\u0119ci podr\u0119cznej drugiego poziomu w przysz\u0142ych procesorach Intela","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

W bazie danych test\u00f3w wydajno\u015bci SiSoftware znaleziono wpis dotycz\u0105cy testowania serwera lub stacji roboczej zbudowanej na dw\u00f3ch tajemniczych sze\u015bciordzeniowych procesorach Intela. Te procesory s\u0105 interesuj\u0105ce przede wszystkim ze wzgl\u0119du na do\u015b\u0107 nietypow\u0105 ilo\u015b\u0107 pami\u0119ci podr\u0119cznej drugiego poziomu \u2013 1,25 MB na rdze\u0144.<\/p>\n

\"Wycieki<\/p>\n

To pi\u0119\u0107 razy wi\u0119cej w por\u00f3wnaniu z 256 KB pami\u0119ci podr\u0119cznej L2 w procesorach desktopowych Coffee Lake Refresh, a tak\u017ce dwa i p\u00f3\u0142 razy wi\u0119cej ni\u017c w najnowszych chipach Ice Lake-U, kt\u00f3re maj\u0105 512 KB na rdze\u0144. To tak\u017ce o 25% wi\u0119cej ni\u017c aktualne procesory HEDT Core-X lub serwerowe Xeon Scalable, kt\u00f3re maj\u0105 po 1 MB pami\u0119ci podr\u0119cznej drugiego poziomu na rdze\u0144.<\/p>\n

\"Wycieki<\/p>\n

Dlatego mo\u017cemy wyci\u0105gn\u0105\u0107 wniosek, \u017ce ten procesor wykorzystuje jedn\u0105 z nowych architektur Intela. Mog\u0105 to by\u0107 10-nm Ice Lake lub Tiger Lake, lub 14-nm Rocket Lake. O dw\u00f3ch ostatnich architekturach jak na razie nie wiadomo zbyt wiele, jednak jedna z niedawnych przeciek\u00f3w<\/a><\/noindex> o Tiger Lake wskazywa\u0142a w\u0142a\u015bnie na obecno\u015b\u0107 1,25 MB pami\u0119ci podr\u0119cznej drugiego poziomu na ka\u017cde rdze\u0144.<\/p>\n

Jednocze\u015bnie, inny przeciek<\/a><\/noindex> wskazywa\u0142a, \u017ce w rodzinie Tiger Lake b\u0119d\u0105 oferowane tylko mobilne procesory z maksymalnie czterema rdzeniami. Z drugiej strony, uk\u0142ady Rocket Lake zaoferuj\u0105 do o\u015bmiu rdzeni. Co wi\u0119cej, przetestowane w SiSoftware sze\u015bciordzeniowe uk\u0142ady maj\u0105 mniej pami\u0119ci podr\u0119cznej trzeciego poziomu ni\u017c wcze\u015bniej \u201ewyciek\u0142y\u201d Tiger Lake.<\/p>\n

<\/center><\/p>\n

Mo\u017cna zatem przypuszcza\u0107, \u017ce mniejsza ilo\u015b\u0107 pami\u0119ci podr\u0119cznej L3 mo\u017ce by\u0107 wynikiem mniej g\u0119stego rozmieszczenia tranzystor\u00f3w, co oznacza bardziej \u201egruby\u201d proces technologiczny. Nie mo\u017cna wykluczy\u0107, \u017ce mamy tutaj do czynienia z przeniesieniem architektury z bardziej \u201ecie\u0144szego\u201d procesu technologicznego 10 nm na stary dobry proces 14 nm. Niedawno w\u0142a\u015bnie zg\u0142aszano<\/a><\/noindex>, \u017ce Rocket Lake b\u0119dzie korzysta\u0107 z nowej architektury, ale w starym procesie technologicznym.<\/p>\n

\"Wycieki<\/p>\n

Jest i inna mo\u017cliwo\u015b\u0107: wszystko, co opisano w dw\u00f3ch poprzednich akapitach, nie spe\u0142ni oczekiwa\u0144, a przed nami system oparty na dw\u00f3ch 10-nm serwerowych procesorach Ice Lake-SP. Mog\u0105 one mie\u0107 te same rdzenie co mobilne Ice Lake-U, ale na ka\u017cde rdze\u0144 przypadnie wi\u0119cej pami\u0119ci podr\u0119cznej drugiego poziomu. Dla Intela taka praktyka nie jest nowo\u015bci\u0105.<\/p>\n

Og\u00f3lnie rzecz bior\u0105c, trudno wyci\u0105gn\u0105\u0107 jakiekolwiek konkretne wnioski na podstawie tego wyniku. Jak wida\u0107, mo\u017cliwo\u015bci s\u0105 liczne, a dowod\u00f3w ma\u0142o. Jedyna rzecz, co do kt\u00f3rej mo\u017cna by\u0107 pewnym \u2013 te sze\u015bciordzeniowe procesory nie s\u0105 pochodnymi Skylake.<\/p>\n

<\/p>\n

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\u0179r\u00f3d\u0142o: 3dnews.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u0412 \u0431\u0430\u0437\u0435 \u0434\u0430\u043d\u043d\u044b\u0445 \u0442\u0435\u0441\u0442\u0430 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438 SiSoftware \u043e\u0431\u043d\u0430\u0440\u0443\u0436\u0438\u043b\u0430\u0441\u044c \u0437\u0430\u043f\u0438\u0441\u044c \u043e \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0438 \u0441\u0435\u0440\u0432\u0435\u0440\u0430 \u0438\u043b\u0438 \u0440\u0430\u0431\u043e\u0447\u0435\u0439 \u0441\u0442\u0430\u043d\u0446\u0438\u0438, \u043f\u043e\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u043e\u0439 \u043d\u0430 \u0434\u0432\u0443\u0445 \u0437\u0430\u0433\u0430\u0434\u043e\u0447\u043d\u044b\u0445 \u0448\u0435\u0441\u0442\u0438\u044f\u0434\u0435\u0440\u043d\u044b\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430\u0445 Intel. \u0414\u0430\u043d\u043d\u044b\u0435 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u044b 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[…]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-54142","post","type-post","status-publish","format-standard","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Wycieki potwierdzaj\u0105 zwi\u0119kszenie pami\u0119ci podr\u0119cznej drugiego poziomu w nadchodz\u0105cych procesorach Intel | ProHoster","description":"W bazie danych test\u00f3w wydajno\u015bci SiSoftware pojawi\u0142 si\u0119 wpis dotycz\u0105cy testowania serwera lub stacji roboczej zbudowanej na dw\u00f3ch tajemniczych sze\u015bciordzeniowych procesorach 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