{"id":111945,"date":"2023-12-03T15:10:13","date_gmt":"2023-12-03T13:10:13","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/vypusk-coreboot-4-22"},"modified":"2023-12-03T15:10:13","modified_gmt":"2023-12-03T13:10:13","slug":"vypusk-coreboot-4-22","status":"publish","type":"post","link":"https:\/\/prohoster.info\/pt\/blog\/news\/vypusk-coreboot-4-22","title":{"rendered":"Lan\u00e7amento do Coreboot 4.22","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"<p>Est\u00e1 dispon\u00edvel a vers\u00e3o 4.22 do projeto CoreBoot, que desenvolve uma alternativa livre a firmware e BIOS propriet\u00e1rios. O c\u00f3digo do projeto \u00e9 distribu\u00eddo sob a licen\u00e7a GPLv2. 135 desenvolvedores contribu\u00edram para a cria\u00e7\u00e3o desta nova vers\u00e3o, que incluiu 977 mudan\u00e7as. \u00c9 destacado que, a partir da pr\u00f3xima vers\u00e3o, o projeto mudar\u00e1 para um novo esquema de nomenclatura que usar\u00e1 uma refer\u00eancia \u00e0 data (ano.m\u00eas.atualiza\u00e7\u00e3o); por exemplo, em fevereiro de 2024, em vez da vers\u00e3o 4.23, ser\u00e1 lan\u00e7ado o vers\u00e3o 24.02.00.      <\/p>\n<p>Principais mudan\u00e7as:   <\/p>\n<ul>\n<li class=\"l\"> Adicionada a implementa\u00e7\u00e3o inicial da plataforma AMD openSIL (Open-Source Silicon Initialization Library), que desenvolve componentes para facilitar a cria\u00e7\u00e3o de firmwares.\n<li class=\"l\"> Suporte adicionado para 17 placas-m\u00e3e. 11 das placas adicionadas s\u00e3o utilizadas em dispositivos com Chrome OS ou em <a class=\"wpil_keyword_link\" href=\"https:\/\/prohoster.info\/pt\/server\/dts-gdansk\/\"   title=\"servidores\" data-wpil-keyword-link=\"linked\"  data-wpil-monitor-id=\"4549\">servidores<\/a> Google. Placas n\u00e3o relacionadas ao Google:\n<ul>\n<li class=\"l\"> AMD Onyx\n<li class=\"l\"> Intel Meteorlake-P RVP\n<li class=\"l\"> Purism Librem 11\n<li class=\"l\"> Purism Librem L1UM v2\n<li class=\"l\"> Siemens FA EHL\n<li class=\"l\"> Supermicro X11SSW-F  <\/ul>\n<li class=\"l\"> Suporte para o SoC AMD Genoa adicionado.\n<li class=\"l\"> Na arquitetura x86, nas fases anteriores \u00e0 inicializa\u00e7\u00e3o da mem\u00f3ria, foi implementado suporte para a se\u00e7\u00e3o &#171;.data&#187;, permitindo o uso de defini\u00e7\u00f5es de vari\u00e1veis globais no c\u00f3digo em linguagem C. Na fase do bloco de inicializa\u00e7\u00e3o, os dados s\u00e3o anexados imediatamente ap\u00f3s o c\u00f3digo e, em seguida, s\u00e3o alocados no cache, utilizando o conceito Cache-As-RAM (VMA).\n<li class=\"l\"> Para sistemas x86, na fase ramstage e em etapas at\u00e9 a inicializa\u00e7\u00e3o da mem\u00f3ria, foi implementado suporte ao cache para o sistema de arquivos CBFS, utilizado para armazenar componentes do Coreboot no Flash. O cache CBFS permite descompactar arquivos CBFS utilizando a fun\u00e7\u00e3o cbfs_map() sem reservar uma \u00e1rea separada de mem\u00f3ria para o arquivo. Para configurar o tamanho do cache, foram propostas as op\u00e7\u00f5es PRERAM_CBFS_CACHE_SIZE e RAMSTAGE_CBFS_CACHE_SIZE.\n<li class=\"l\"> Adicionada a possibilidade de incorporar romstage no bloco de inicializa\u00e7\u00e3o (bootblock). A entrega do romstage como parte do bloco de inicializa\u00e7\u00e3o permite reduzir o tamanho do c\u00f3digo em 10 a 20 mil linhas. Entre as situa\u00e7\u00f5es em que uma entrega separada do romstage pode ser necess\u00e1ria est\u00e3o as configura\u00e7\u00f5es com vboot ou modo fallback, bem como dispositivos com tamanho limitado do bloco de inicializa\u00e7\u00e3o (Intel APL 32K) ou meio de inicializa\u00e7\u00e3o muito lento (alguns SoCs ARM).\n<li class=\"l\"> No gfx, foi adicionado um API para detectar a presen\u00e7a de uma tela externa em dispositivos com chips Intel.\n<li class=\"l\"> No pci_rom, foi implementada a capacidade de adicionar uma soma de verifica\u00e7\u00e3o para o VBIOS ao preencher a tabela VFCT. Essa soma de verifica\u00e7\u00e3o \u00e9 verificada por alguns drivers AMD para Windows.\n<li class=\"l\"> Foram feitas altera\u00e7\u00f5es que permitem executar o Windows em alguns dispositivos Chromebook com Coreboot.\n<li class=\"l\"> Implementada a gera\u00e7\u00e3o da tabela ACPI para dispositivos baseados na arquitetura ARM64.\n<li class=\"l\"> Melhorada a compatibilidade com as especifica\u00e7\u00f5es ACPI.\n<li class=\"l\"> As configura\u00e7\u00f5es do MRC (Memory Reference Code) para placas SNB+MRC foram transferidas para a estrutura DeviceTree.\n<li class=\"l\"> Atualizados os componentes do payload baseados em U-Boot e edk2.\n<li class=\"l\"> Atualizada a ferramenta utilizada: GMP 6.3.0, binutils 2.41 e MPFR 4.2.1.\n<li class=\"l\"> O ramo principal no reposit\u00f3rio Git foi renomeado de &#171;master&#187; para &#171;main&#187;.  <\/ul>\n<p>Fonte: <a content=\"nofollow\" rel=\"nofollow\" href=\"https:\/\/www.opennet.ru\/opennews\/art.shtml?num=60224\">opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"<p>\u0414\u043e\u0441\u0442\u0443\u043f\u0435\u043d \u0440\u0435\u043b\u0438\u0437 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 CoreBoot 4.22, \u0432 \u0440\u0430\u043c\u043a\u0430\u0445 \u043a\u043e\u0442\u043e\u0440\u043e\u0433\u043e \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441\u0432\u043e\u0431\u043e\u0434\u043d\u0430\u044f \u0430\u043b\u044c\u0442\u0435\u0440\u043d\u0430\u0442\u0438\u0432\u0430 \u043f\u0440\u043e\u043f\u0440\u0438\u0435\u0442\u0430\u0440\u043d\u044b\u043c \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0430\u043c \u0438 BIOS. \u041a\u043e\u0434 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u0435\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 GPLv2. \u0412 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0438 \u043d\u043e\u0432\u043e\u0439 \u0432\u0435\u0440\u0441\u0438\u0438 \u043f\u0440\u0438\u043d\u044f\u043b\u043e \u0443\u0447\u0430\u0441\u0442\u0438\u0435 135 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u0432, \u043a\u043e\u0442\u043e\u0440\u044b\u0435 \u043f\u043e\u0434\u0433\u043e\u0442\u043e\u0432\u0438\u043b\u0438 977 \u0438\u0437\u043c\u0435\u043d\u0435\u043d\u0438\u0439. \u041e\u0442\u043c\u0435\u0447\u0430\u0435\u0442\u0441\u044f, \u0447\u0442\u043e \u043d\u0430\u0447\u0438\u043d\u0430\u044f \u0441\u043e \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0435\u0433\u043e \u0432\u044b\u043f\u0443\u0441\u043a\u0430 \u043f\u0440\u043e\u0435\u043a\u0442 \u043f\u0435\u0440\u0435\u0439\u0434\u0451\u0442 \u043d\u0430 \u043d\u043e\u0432\u0443\u044e \u0441\u0445\u0435\u043c\u0443 \u043d\u0430\u0438\u043c\u0435\u043d\u043e\u0432\u0430\u043d\u0438\u044f \u0432\u0435\u0440\u0441\u0438\u0439, \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044e\u0449\u0443\u044e \u043f\u0440\u0438\u0432\u044f\u0437\u043a\u0443 \u043a \u0434\u0430\u0442\u0435 (\u0433\u043e\u0434.\u043c\u0435\u0441\u044f\u0446.\u043e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u0435), \u043d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, \u0432 \u0444\u0435\u0432\u0440\u0430\u043b\u0435 2024 [&hellip;]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-111945","post","type-post","status-publish","format-standard","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.3 - 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