A AMD incluiu os processadores baseados na microarquitetura Zen 5 na lista de produtos vulner\u00e1veis \u00e0 vulnerabilidade EntrySign, que permite contornar o mecanismo de verifica\u00e7\u00e3o de assinatura digital durante a atualiza\u00e7\u00e3o do microc\u00f3digo. Inicialmente, supunha-se que a vulnerabilidade afetava apenas os CPUs AMD das gera\u00e7\u00f5es 1-4 da microarquitetura Zen. Assim, a vulnerabilidade se mostrou aplic\u00e1vel a processadores como Ryzen 9000 (Granite Ridge), EPYC 9005 (Turin), Ryzen AI 300 (Strix Halo, Strix Point, Krackan Point) e Ryzen 9000HX (Fire Range). <\/p>\n
Al\u00e9m da atualiza\u00e7\u00e3o do microc\u00f3digo, para eliminar a vulnerabilidade em sistemas que utilizam a certifica\u00e7\u00e3o SEV-SNP, tamb\u00e9m \u00e9 necess\u00e1ria a atualiza\u00e7\u00e3o do firmware AMD SEV, que \u00e9 fornecido com as atualiza\u00e7\u00f5es de BIOS. A AMD afirma que enviou aos fabricantes de hardware um firmware modificado (ComboAM5PI 1.2.0.3c AGESA), necess\u00e1rio para resolver o problema, mas as atualiza\u00e7\u00f5es de BIOS finais dispon\u00edveis para os consumidores podem ser lan\u00e7adas pelos fabricantes semanas ou meses depois. <\/p>\n
Funcion\u00e1rios da AMD tamb\u00e9m propuseram a inclus\u00e3o de um patch no kernel do Linux que bloqueia o carregamento de atualiza\u00e7\u00f5es de microc\u00f3digo n\u00e3o oficiais (observa-se que atualiza\u00e7\u00f5es corretas de microc\u00f3digo devem ser instaladas junto com o BIOS do fabricante do hardware, mas j\u00e1 surgiram tentativas de criadores n\u00e3o oficiais de corrigir problemas com base em fragmentos de microc\u00f3digo retirados do BIOS). Os usu\u00e1rios s\u00e3o aconselhados a aguardar as atualiza\u00e7\u00f5es oficiais de BIOS. <\/p>\n
A vulnerabilidade oferecida pelo EntrySign que permite a modifica\u00e7\u00e3o do microc\u00f3digo pode comprometer o mecanismo AMD SEV (Secure Encrypted Virtualization), usado em sistemas de virtualiza\u00e7\u00e3o para prote\u00e7\u00e3o m\u00e1quinas virtuais<\/a> contra interfer\u00eancia por parte do hypervisor ou do administrador do sistema host. Durante um ataque, \u00e9 poss\u00edvel intervir nas opera\u00e7\u00f5es de sistemas convidados protegidos por meio de extens\u00f5es AMD SEV (Secure Encrypted Virtualization) e SEV-SNP (Secure Nested Paging), que garantem a integridade da mem\u00f3ria das m\u00e1quinas virtuais, isolam os registradores do processador e asseguram um funcionamento seguro com tabelas de p\u00e1ginas de mem\u00f3ria aninhadas. <\/p>\n A vulnerabilidade \u00e9 causada pelo uso de um processo de verifica\u00e7\u00e3o do microc\u00f3digo do algoritmo de inser\u00e7\u00e3o de mensagens CMAC em vez de uma fun\u00e7\u00e3o hash confi\u00e1vel. A empresa AMD utiliza uma chave RSA privada para certificar digitalmente o microc\u00f3digo carregado no processador, e, na atualiza\u00e7\u00e3o do microc\u00f3digo, distribui a chave p\u00fablica. Para verificar se a chave p\u00fablica corresponde ao par original de chaves RSA, o processador realiza a compara\u00e7\u00e3o do hash da chave p\u00fablica AMD, embutido durante a produ\u00e7\u00e3o do CPU, com o hash da chave p\u00fablica indicada no patch. <\/p>\n A verifica\u00e7\u00e3o da autenticidade do microc\u00f3digo no patch \u00e9 realizada comparando o hash fornecido com o patch, assinado digitalmente (RSASSA-PKCS1-v1_5), com o hash calculado com base no microc\u00f3digo efetivamente fornecido no patch. Se os hashes de refer\u00eancia e calculado coincidirem \u2014 o patch \u00e9 carregado na mem\u00f3ria interna da CPU. O problema \u00e9 que, em vez de usar fun\u00e7\u00f5es de hash criptograficamente seguras recomendadas, foi aplicado o algoritmo CMAC, que n\u00e3o \u00e9 projetado para tais opera\u00e7\u00f5es e n\u00e3o est\u00e1 protegido contra colis\u00f5es. <\/p>\n CMAC n\u00e3o \u00e9 uma fun\u00e7\u00e3o hash, mas implementa uma inser\u00e7\u00e3o de mensagem (Message Authentication Code), dependente da chave de criptografia. O funcionamento do AES-CMAC envolve o uso do algoritmo criptogr\u00e1fico AES e a combina\u00e7\u00e3o do resultado de sua aplica\u00e7\u00e3o com o pr\u00f3ximo bloco de dados usando a opera\u00e7\u00e3o XOR. Este esquema garante que a altera\u00e7\u00e3o dos dados de entrada resultar\u00e1 em uma mudan\u00e7a imprevis\u00edvel nos dados de sa\u00edda. No entanto, o uso do CMAC como uma fun\u00e7\u00e3o hash \u00e9 inaceit\u00e1vel, pois qualquer um que conhe\u00e7a a chave de criptografia original pode descobrir estados intermedi\u00e1rios de criptografia e calcular valores que possam compensar a altera\u00e7\u00e3o nos dados de entrada, de forma que o resultado da aplica\u00e7\u00e3o do CMAC permane\u00e7a inalterado. <\/p>\n A AMD utiliza uma chave criptogr\u00e1fica \u00fanica para AES-CMAC, fornecida em todas as CPUs, come\u00e7ando com a Zen 1. Assim, \u00e9 suficiente extrair essa chave de qualquer CPU AMD e ela ser\u00e1 aplic\u00e1vel a todas as outras CPUs. Os pesquisadores descobriram que, para a criptografia AES-CMAC, a AMD utilizou uma chave conhecida, retirada de um exemplo mencionado nas diretrizes para o uso de cifras de bloco NIST SP 800-38B. Como o AES-CMAC \u00e9 usado para a hashing da chave RSA embutida em um patch e do conte\u00fado do microc\u00f3digo, ao determinar a chave de criptografia AES-CMAC, surgiu a possibilidade de substituir o patch por outra chave RSA p\u00fablica e alterar o conte\u00fado do microc\u00f3digo. <\/p>\n Para criar um patch falso, basta gerar uma nova chave p\u00fablica que produza o mesmo hash que a chave p\u00fablica real da AMD, al\u00e9m de encontrar colis\u00f5es para a assinatura digital. As colis\u00f5es s\u00e3o formadas anexando ao microc\u00f3digo um bloco adicional que parece um conjunto de dados aleat\u00f3rios. Da mesma forma, \u00e9 poss\u00edvel preparar um patch modificado com o microc\u00f3digo correspondente \u00e0 assinatura digital que autentica o patch original da AMD. O conjunto de ferramentas Zentool, que inclui utilit\u00e1rios para analisar microc\u00f3digos e criar patches para modificar microc\u00f3digos, est\u00e1 dispon\u00edvel sob a licen\u00e7a Apache 2.0. Para substituir o microc\u00f3digo, \u00e9 necess\u00e1rio ter permiss\u00f5es para executar c\u00f3digo em n\u00edvel de anel zero de prote\u00e7\u00e3o (as tecnologias VT-x e AMD-V permitem que o sistema convidado execute com permiss\u00f5es Ring 0). \u041a\u043e\u043c\u043f\u0430\u043d\u0438\u044f AMD \u0432\u043a\u043b\u044e\u0447\u0438\u043b\u0430 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u044b \u043d\u0430 \u0431\u0430\u0437\u0435 \u043c\u0438\u043a\u0440\u043e\u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b Zen 5 \u0432 \u0441\u043f\u0438\u0441\u043e\u043a \u043f\u0440\u043e\u0434\u0443\u043a\u0442\u043e\u0432, \u043f\u043e\u0434\u0432\u0435\u0440\u0436\u0435\u043d\u043d\u044b\u0445 \u0443\u044f\u0437\u0432\u0438\u043c\u043e\u0441\u0442\u0438 EntrySign, \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u044e\u0449\u0435\u0439 \u043e\u0431\u043e\u0439\u0442\u0438 \u043c\u0435\u0445\u0430\u043d\u0438\u0437\u043c \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0438 \u0446\u0438\u0444\u0440\u043e\u0432\u043e\u0439 \u043f\u043e\u0434\u043f\u0438\u0441\u0438 \u043f\u0440\u0438 \u043e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u0438 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u0434\u0430. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u0435\u0434\u043f\u043e\u043b\u0430\u0433\u0430\u043b\u043e\u0441\u044c, \u0447\u0442\u043e \u0443\u044f\u0437\u0432\u0438\u043c\u043e\u0441\u0442\u044c \u0437\u0430\u0442\u0440\u0430\u0433\u0438\u0432\u0430\u0435\u0442 \u0442\u043e\u043b\u044c\u043a\u043e CPU AMD \u043d\u0430 \u0431\u0430\u0437\u0435 1-4 \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u0439 \u043c\u0438\u043a\u0440\u043e\u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b Zen. \u0422\u0430\u043a\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c \u0443\u044f\u0437\u0432\u0438\u043c\u043e\u0441\u0442\u044c \u043e\u043a\u0430\u0437\u0430\u043b\u0430\u0441\u044c \u043f\u0440\u0438\u043c\u0435\u043d\u0438\u043c\u0430 \u043a \u0442\u0430\u043a\u0438\u043c \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430\u043c, \u043a\u0430\u043a Ryzen 9000 (Granite Ridge), EPYC 9005 (Turin), Ryzen […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-123472","post","type-post","status-publish","format-standard","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Processadores AMD Zen 5 est\u00e3o vulner\u00e1veis a altera\u00e7\u00f5es no microc\u00f3digo e aos contornos da isola\u00e7\u00e3o SEV-SNP | ProHoster","description":"A AMD incluiu processadores baseados na microarquitetura Zen 5 na lista de produtos vulner\u00e1veis \u00e0 vulnerabilidade EntrySign, que permite contornar o mecanismo de verifica\u00e7\u00e3o de assinatura digital ao atualizar o microc\u00f3digo.","canonical_url":"https:\/\/prohoster.info\/pt\/blog\/news\/cpu-amd-zen-5-podverzheny-uyazvimosti-dopuskayushhej-izmenenie-mikrokoda-i-obhod-izolyaczii-sev-snp","robots":"max-image-preview:large","keywords":"","webmasterTools":{"miscellaneous":""},"schema":null,"og:locale":"pt_PT","og:site_name":"ProHoster | \u041a\u0443\u043f\u0438\u0442\u044c \u043d\u0430\u0434\u0435\u0436\u043d\u044b\u0439 \u0445\u043e\u0441\u0442\u0438\u043d\u0433 \u0434\u043b\u044f \u0441\u0430\u0439\u0442\u043e\u0432 \u0441 \u0437\u0430\u0449\u0438\u0442\u043e\u0439 \u043e\u0442 DDoS, VPS VDS \u0441\u0435\u0440\u0432\u0435\u0440\u044b","og:type":"article","og:title":"\ud83e\udd47CPU AMD Zen 5 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Fonte: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"