{"id":30179,"date":"2019-10-31T21:34:00","date_gmt":"2019-10-31T18:34:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski\/"},"modified":"2019-10-31T21:34:00","modified_gmt":"2019-10-31T18:34:00","slug":"asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski","status":"publish","type":"post","link":"https:\/\/prohoster.info\/pt\/blog\/asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski","title":{"rendered":"ASIC para aprendizado de m\u00e1quina deve ser projetado automaticamente","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\u00c9 dif\u00edcil que algu\u00e9m discorde que o projeto de circuitos integrados espec\u00edficos para aplica\u00e7\u00f5es (ASIC) n\u00e3o \u00e9 um processo simples e r\u00e1pido. No entanto, \u00e9 desej\u00e1vel acelerar esse processo: hoje, um algoritmo \u00e9 gerado e, na semana seguinte, um projeto digital pronto \u00e9 retirado. O fato \u00e9 que os ASIC superespecializados s\u00e3o quase produtos \u00fanicos. Eles raramente s\u00e3o \u00fateis em grandes quantidades, nas quais se pode investir qualquer quantia de dinheiro e recursos humanos, se for necess\u00e1rio faz\u00ea-lo rapidamente. ASIC especializados, e por isso mais eficazes para resolver suas tarefas, devem ser desenvolvidos a um custo menor, o que se torna extremamente relevante na fase atual de desenvolvimento do aprendizado de m\u00e1quina. Nesse campo, j\u00e1 n\u00e3o podemos contar apenas com o conhecimento acumulado pelo mercado de computadores e, especialmente, com os avan\u00e7os em unidades de processamento gr\u00e1fico (GPU) na \u00e1rea do aprendizado de m\u00e1quina (ML).<\/p>\n

\"ASIC<\/p>\n

Para acelerar o projeto de ASIC para tarefas de ML, a ag\u00eancia DARPA criou um novo programa - Aprendizado de M\u00e1quina em Tempo Real (RTML). O programa de aprendizado de m\u00e1quina em tempo real prev\u00ea o desenvolvimento de um compilador ou plataforma de software capaz de projetar automaticamente a arquitetura do chip para um determinado framework de ML. A plataforma deve analisar automaticamente o algoritmo proposto para aprendizado de m\u00e1quina e o conjunto de dados de treinamento para esse algoritmo, ap\u00f3s o que, em Verilog, deve gerar o c\u00f3digo para criar um ASIC especializado. Especialistas em desenvolvimento de algoritmos de ML n\u00e3o possuem conhecimentos de projetistas de chips, e os projetistas raramente est\u00e3o familiarizados com os princ\u00edpios de aprendizado de m\u00e1quina. O programa RTML deve facilitar a fus\u00e3o das vantagens de ambos em uma plataforma automatizada de desenvolvimento de ASIC para aprendizado de m\u00e1quina.<\/p>\n

Durante o ciclo de vida do programa RTML, as solu\u00e7\u00f5es encontradas dever\u00e3o ser testadas em duas principais \u00e1reas de aplica\u00e7\u00e3o: opera\u00e7\u00e3o em redes 5G e processamento de imagens. Al\u00e9m disso, o programa RTML e as plataformas de software criadas para o design automatizado de aceleradores de ML ser\u00e3o utilizados para desenvolver e testar novos algoritmos de ML e conjuntos de dados. Assim, mesmo antes do design do 'sil\u00edcio', ser\u00e1 poss\u00edvel avaliar as perspectivas das novas estruturas. O parceiro da DARPA no programa RTML ser\u00e1 a Funda\u00e7\u00e3o Nacional de Ci\u00eancias (NSF), que tamb\u00e9m est\u00e1 lidando com quest\u00f5es de aprendizado de m\u00e1quina e desenvolvimento de algoritmos de ML. O compilador desenvolvido ser\u00e1 entregue \u00e0 NSF, enquanto a DARPA espera receber de volta o compilador e a plataforma para o design de algoritmos de ML. No futuro, o design de hardware e a cria\u00e7\u00e3o de algoritmos ser\u00e3o uma solu\u00e7\u00e3o integrada, levando ao surgimento de sistemas de m\u00e1quinas aut\u00f4nomas em tempo real.<\/p>\n

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Fonte: 3dnews.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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