{"id":33621,"date":"2019-10-31T21:53:47","date_gmt":"2019-10-31T18:53:47","guid":{"rendered":"https:\/\/prohoster.info\/blog\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620\/"},"modified":"2019-10-31T21:53:47","modified_gmt":"2019-10-31T18:53:47","slug":"additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","status":"publish","type":"post","link":"https:\/\/prohoster.info\/pt\/blog\/administrirovanie\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","title":{"rendered":"Uplinks adicionais na arquitetura da l\u00f3gica de sistema Intel C620","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Na arquitetura das plataformas x86, surgiram duas correntes que se complementam mutuamente. De acordo com uma vers\u00e3o, \u00e9 necess\u00e1rio avan\u00e7ar na dire\u00e7\u00e3o da integra\u00e7\u00e3o de recursos computacionais e de controle em um \u00fanico cristal. A segunda abordagem defende a distribui\u00e7\u00e3o de fun\u00e7\u00f5es: o processador \u00e9 equipado com um barramento de alta performance, formando um ecossistema escal\u00e1vel perif\u00e9rico. Esta abordagem \u00e9 a base da topologia da l\u00f3gica do sistema Intel C620 para plataformas de alto n\u00edvel.<\/a><\/noindex><\/p>\n

A diferen\u00e7a fundamental em rela\u00e7\u00e3o ao chipset anterior Intel C610 \u00e9 a amplia\u00e7\u00e3o do canal de comunica\u00e7\u00e3o entre o processador e a periferia, que faz parte do chip PCH, atrav\u00e9s da utiliza\u00e7\u00e3o de links PCIe juntamente com o tradicional barramento DMI.<\/p>\n

\"Uplinks
\n
\nVamos analisar mais detalhadamente as inova\u00e7\u00f5es do ponte sul Intel Lewisburg: quais abordagens evolutivas e revolucion\u00e1rias ampliaram suas compet\u00eancias na comunica\u00e7\u00e3o com os processadores?<\/p>\n

Mudan\u00e7as evolutivas na comunica\u00e7\u00e3o CPU-PCH<\/h2>\n

\nNo \u00e2mbito da abordagem evolutiva, o principal canal de comunica\u00e7\u00e3o entre a CPU e o ponte sul, que \u00e9 o barramento DMI (Direct Media Interface), recebeu suporte para o modo PCIe x4 Gen3 com uma performance de 8.0 GT\/S. Anteriormente, no Intel C610 PCH, a comunica\u00e7\u00e3o entre o processador e a l\u00f3gica do sistema acontecia no modo PCIe x4 Gen 2 com uma largura de banda de 5.0 GT\/S.<\/p>\n

\"Uplinks
\n
\nCompara\u00e7\u00e3o da funcionalidade da l\u00f3gica do sistema Intel C610 e C620<\/em><\/p>\n

Observe que este subsistema \u00e9 significativamente mais conservador do que as portas PCIe embutidas do processador, normalmente utilizadas para conectar GPUs e unidades NVMe, onde o PCIe 3.0 j\u00e1 \u00e9 aplicado h\u00e1 algum tempo e a transi\u00e7\u00e3o para o PCI Express Gen4 est\u00e1 em andamento.<\/p>\n

Mudan\u00e7as revolucion\u00e1rias na comunica\u00e7\u00e3o CPU-PCH<\/h2>\n

\nMudan\u00e7as revolucion\u00e1rias incluem a adi\u00e7\u00e3o de novos canais PCIe de comunica\u00e7\u00e3o CPU-PCH, chamados de Additional Uplinks. Fisicamente, s\u00e3o duas portas PCI Express operando nos modos PCIe x8 Gen3 e PCIe x16 Gen3, ambas a 8.0 GT\/S.<\/p>\n

\"Uplinks
\n
\nPara a intera\u00e7\u00e3o entre a CPU e o Intel C620 PCH, s\u00e3o utilizados 3 barramentos: DMI e duas portas PCI Express<\/em><\/p>\n

Por que houve a necessidade de revisar a topologia existente de comunica\u00e7\u00f5es com o Intel C620? Primeiro, o PCH pode integrar at\u00e9 4 controladores de rede 10GbE com funcionalidade RDMA. Em segundo lugar, a nova e mais r\u00e1pida gera\u00e7\u00e3o de coprocessadores Intel QuickAssist Technology (QAT) \u00e9 respons\u00e1vel pela criptografia do tr\u00e1fego de rede e pela troca com o subsistema de armazenamento, oferecendo suporte de hardware para compress\u00e3o e criptografia. E, por fim, o \"motor de inova\u00e7\u00e3o\" \u2014 Innovation Engine<\/a><\/noindex>, que estar\u00e1 dispon\u00edvel apenas para fabricantes OEM.<\/p>\n

Escalabilidade e flexibilidade<\/h2>\n

\nUma caracter\u00edstica importante \u00e9 a capacidade de selecionar opcionalmente n\u00e3o apenas a topologia da conex\u00e3o PCH, mas tamb\u00e9m as prioridades dos recursos internos do chip no acesso aos canais de comunica\u00e7\u00e3o de alta velocidade com o processador (processadores). Al\u00e9m disso, no modo especial EPO (EndPoint Only Mode), a conex\u00e3o PCH \u00e9 realizada no status de um dispositivo PCI Express normal, contendo os recursos de 10 GbE e Intel QAT. Neste caso, a interface cl\u00e1ssica DMI, bem como uma s\u00e9rie de subsistemas Legacy, mostrados no diagrama em preto, s\u00e3o desativados.<\/p>\n

\"Uplinks
\n
\nArquitetura interna do chip Intel C620 PCH<\/em><\/p>\n

Teoricamente, isso permite o uso de mais de um chip Intel C620 PCH no sistema, escalando a funcionalidade de 10 GbE e Intel QAT de acordo com as exig\u00eancias de desempenho. As fun\u00e7\u00f5es Legacy, que s\u00e3o necess\u00e1rias apenas em uma \u00fanica inst\u00e2ncia, podem ser ativadas apenas em um dos chips PCH instalados.<\/p>\n

Assim, a palavra final no design pertencer\u00e1 ao desenvolvedor da plataforma, que atuar\u00e1 com base em fatores tecnol\u00f3gicos e de marketing, de acordo com o posicionamento de cada produto espec\u00edfico.
\n
Fonte: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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Segundo uma vers\u00e3o, \u00e9 necess\u00e1rio avan\u00e7ar em dire\u00e7\u00e3o \u00e0 integra\u00e7\u00e3o dos recursos computacionais e de controle em um \u00fanico cristal.","canonical_url":"https:\/\/prohoster.info\/pt\/blog\/administrirovanie\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","robots":"max-image-preview:large","keywords":"","webmasterTools":{"miscellaneous":""},"schema":null,"og:locale":"pt_PT","og:site_name":"ProHoster | \u041a\u0443\u043f\u0438\u0442\u044c \u043d\u0430\u0434\u0435\u0436\u043d\u044b\u0439 \u0445\u043e\u0441\u0442\u0438\u043d\u0433 \u0434\u043b\u044f \u0441\u0430\u0439\u0442\u043e\u0432 \u0441 \u0437\u0430\u0449\u0438\u0442\u043e\u0439 \u043e\u0442 DDoS, VPS VDS \u0441\u0435\u0440\u0432\u0435\u0440\u044b","og:type":"article","og:title":"\ud83e\udd47Additional Uplinks \u0432 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0435 \u0441\u0438\u0441\u0442\u0435\u043c\u043d\u043e\u0439 \u043b\u043e\u0433\u0438\u043a\u0438 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