{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/ro\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"Proiectul VeriGPU dezvolt\u0103 un GPU deschis \u00een limbajul Verilog","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Proiectul VeriGPU are ca scop crearea unui GPU deschis, dezvoltat pe baza limbajului de descriere \u0219i modelare a sistemelor electronice Verilog. Ini\u021bial, proiectul este dezvoltat utiliz\u00e2nd un simulator Verilog, dar, dup\u0103 ce va fi finalizat, va putea fi utilizat pentru producerea de cipuri reale. Dezvolt\u0103rile proiectului sunt distribuite sub licen\u021ba MIT. <\/p>\n

VeriGPU este pozi\u021bionat ca un procesor specializat (ASIC), optimizat pentru accelerarea calculelor legate de sistemele de \u00eenv\u0103\u021bare automat\u0103. Planurile men\u021bioneaz\u0103 asigurarea compatibilit\u0103\u021bii cu cadrul de \u00eenv\u0103\u021bare profund\u0103 PyTorch \u0219i implementarea posibilit\u0103\u021bii de a dezvolta aplica\u021bii pentru VeriGPU folosind API HIP (Heterogeneous-Compute Interface). \u00cen viitor, nu se exclude ad\u0103ugarea suportului pentru alte API-uri, cum ar fi SYCL \u0219i NVIDIA CUDA. <\/p>\n

GPU-ul se dezvolt\u0103 pe baza unui set de instruc\u021biuni RISC-V, dar arhitectura intern\u0103 final\u0103 a setului de instruc\u021biuni GPU este slab compatibil\u0103 cu RISC-V ISA, deoarece \u00een situa\u021biile \u00een care proiectarea GPU-ului nu se aliniaz\u0103 cu specifica\u021biile RISC-V, nu se urm\u0103re\u0219te men\u021binerea compatibilit\u0103\u021bii cu RISC-V. Dezvoltarea se concentreaz\u0103 pe capacit\u0103\u021bile necesare pentru sistemele de \u00eenv\u0103\u021bare automat\u0103, motiv pentru care, pentru a reduce dimensiunea \u0219i complexitatea matricei cipului, este utilizat doar formatul de calcul \u00een virgul\u0103 mobil\u0103 BF16, iar doar opera\u021biile \u00een virgul\u0103 mobil\u0103 solicitate pentru \u00eenv\u0103\u021barea automat\u0103 sunt disponibile, cum ar fi exp, log, tanh \u0219i sqrt. <\/p>\n

Printre componentele deja disponibile se num\u0103r\u0103 controlerul GPU, APU (Unitate de procesare accelerat\u0103) pentru opera\u021bii \u00eentregi («+»,»-«,»\\\/»,»*»), un bloc pentru opera\u021bii cu punct flotant («+»,»*») \u0219i un bloc de asigurare a ramifica\u021biei. Pentru dezvoltarea aplica\u021biilor, se ofer\u0103 asamblare \u0219i suport pentru compilarea codului \u00een C++ bazat pe LLVM. Printre func\u021bionalit\u0103\u021bile planificate se remarc\u0103 execu\u021bia paralel\u0103 a instruc\u021biunilor, cache-ul pentru date \u0219i instruc\u021biuni \u0219i opera\u021biile SIMT (Instruc\u021biune unic\u0103 pentru multiple fire de execu\u021bie).

\"Proiectul<\/center>
\n
Sursa: opennet.ro<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103861,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103860","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Proiectul VeriGPU dezvolt\u0103 un GPU deschis pe limbajul Verilog | ProHoster","description":"Proiectul VeriGPU are ca scop crearea unui GPU deschis, dezvoltat pe baza limbajului de descriere \u0219i modelare a sistemelor electronice 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