{"id":181998,"date":"2026-06-10T02:48:19","date_gmt":"2026-06-10T00:48:19","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/opublikovan-vortex-3-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v"},"modified":"2026-06-10T02:48:19","modified_gmt":"2026-06-10T00:48:19","slug":"opublikovan-vortex-3-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/ro\/blog\/news\/opublikovan-vortex-3-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","title":{"rendered":"A fost lansat Vortex 3.0, un GPGPU deschis bazat pe arhitectura RISC-V","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"<p>Este disponibil\u0103 versiunea proiectului Vortex 3.0, care dezvolt\u0103 un GPGPU deschis bazat pe arhitectura setului de instruc\u021biuni RISC-V, destinat execut\u0103rii calculilor paralele utiliz\u00e2nd API-ul OpenCL \u0219i modelul de execu\u021bie SIMT (Single Instruction, Multiple Threads). Proiectul poate fi utilizat, de asemenea, \u00een cercet\u0103ri \u00een domeniul graficii 3D \u0219i \u00een dezvoltarea unor noi arhitecturi GPU. Schemele, descrierile blocurilor hardware \u00een Verilog, simulatorul, driverele \u0219i documenta\u021bia asociat\u0103 proiectului sunt distribuite sub licen\u021ba Apache 2.0. <\/p>\n<p>Fundamentul GPGPU este un ISA RISC-V standard, extins cu instruc\u021biuni suplimentare pentru a sprijini func\u021biile GPU \u0219i gestionarea fluxurilor. Modific\u0103rile arhitecturii setului de instruc\u021biuni RISC-V sunt minime \u0219i, acolo unde este posibil, se folosesc instruc\u021biuni vectoriale existente. Printre instruc\u021biunile suplimentare se num\u0103r\u0103: \u00abtex\u00bb pentru accelerarea proces\u0103rii texturilor; vx_rast pentru controlul rasteriz\u0103rii, vx_rop pentru procesarea fragmentelor, ad\u00e2ncimii \u0219i transparen\u021bei; vx_imadd pentru efectuarea opera\u021biei \u00ab\u00eenmul\u021bire \u0219i adunare\u00bb; vx_wspawn, vx_split, vx_join, vx_tmc \u0219i vx_bar pentru activarea grupurilor de fluxuri (wavefronts), executate \u00een paralel de SIMD Engine. <\/p>\n<p><center><img decoding=\"async\" src=\"\/wp-content\/uploads\/2026\/06\/caa6274ce0dd622a2ebc01d60302d645.png\" style=\"display:block;margin: 0 auto;\" \/><\/center><\/p>\n<p>GPGPU-ul dezvoltat suport\u0103 arhitecturi de set de instruc\u021biuni RISC-V de 32 \u0219i 64 de bi\u021bi, RV32IMF \u0219i RV64IMAFD, \u0219i poate include memorie partajat\u0103 op\u021bional\u0103, cache-uri L1, L2 \u0219i L3, precum \u0219i un num\u0103r configurabil de nuclee, blocuri de sarcini (warps) \u0219i fluxuri. \u00cen plus, pentru fiecare nucleu este prev\u0103zut\u0103 posibilitatea de a activa un num\u0103r configurabil de ALU, FPU, LSU \u0219i SFU. Pentru prototipare pot fi utilizate FPGA Xilinx \u0219i Altera, iar pentru simularea func\u021bion\u0103rii cipului se pot folosi Verilator (simulator Verilog), RTLSIM (simularea RTL) \u0219i SimX (simularea software).<\/p>\n<p>Pentru dezvoltarea aplica\u021biilor se ofer\u0103 un set de instrumente, inclusiv variante adaptate pentru lucru cu Vortex din PoCL (compiler \u0219i runtime OpenCL), LLVM\/Clang, GCC \u0219i Binutils. Proiectul suport\u0103 specifica\u021bia OpenCL 1.2 \u0219i prin transla\u021bie \u00een OpenCL se implementeaz\u0103 suportul pentru reprezentarea intermediar\u0103 a shader-elor SPIR-V.  <\/p>\n<p>Printre schimb\u0103rile din Vortex 3.0:<\/p>\n<ul>\n<li class=\"l\"> A fost ad\u0103ugat un stiv\u0103 grafic\u0103 hardware, incluz\u00e2nd module pentru rasterizare, suprapunerea texturilor \u0219i fuziunea ie\u0219irii (OM \u2014 Output Merger). Pentru Mesa bazat\u0103 pe stiva grafic\u0103 implementat\u0103 \u0219i rasterizatorul software lavapipe a fost preg\u0103tit driverul Vulkan vortexpipe.\n<li class=\"l\"> Capacit\u0103\u021bile nucleului tensor au fost extinse, destinat acceler\u0103rii execu\u021biei modelelor de \u00eenv\u0103\u021bare automat\u0103, \u00een care este implementat suportul pentru sparsitate structural\u0103 (structured sparsity) pentru comprimarea matricelor de greutate.\n<li class=\"l\"> A fost implementat\u0103 opera\u021bia WGMMA (\u00eenmul\u021birea matricelor la nivel warpgroup) pentru \u00eenmul\u021birea matricelor \u00een mod asincron.\n<li class=\"l\"> A fost ad\u0103ugat motorul DXA (Accelerarea Transferului de Date) pentru a accelera transferul de date din memoria global\u0103 \u00een memoria local\u0103.\n<li class=\"l\"> A fost implementat\u0103 o nou\u0103 arhitectur\u0103 bazat\u0103 pe procesorul de comenzi (CP, Command Processor) \u0219i un planificator hardware pentru nucleele de calcul (KMU \u2014 Kernel Management Unit), care permite desf\u0103\u0219urarea opera\u021biunilor de gestionare a fluxurilor de calcul pe cip.\n<li class=\"l\"> A fost propus\u0103 o nou\u0103 bibliotec\u0103 runtime, care func\u021bioneaz\u0103 \u00een mod neblocat \u0219i ofer\u0103 abstractiz\u0103ri, traduse \u00een comenzi hardware executate asincron. Sunt suportate cozi, evenimente, module \u0219i sincronizare bazat\u0103 pe barierele asincrone cu semantica arrive\/wait\/event.\n<li class=\"l\"> A fost ad\u0103ugat suport pentru instruc\u021biuni scurte RISC-V (RVC).\n<li class=\"l\"> A fost implementat suport hardware pentru opera\u021bii atomice (Hardware Atomics).\n<li class=\"l\"> FPU a fost complet reproiectat \u0219i au fost propuse noi blocuri de multiplicatori (Wallace-tree, Folded-radix) \u0219i adun\u0103tori (Kogge-Stone).\n<li class=\"l\"> A fost ad\u0103ugat un stiv\u0103 de memorie virtual\u0103 bazat\u0103 pe blocul de control al memoriei (MMU) cu suport pentru arhitectura de adresare virtual\u0103 de 32 de bi\u021bi SV32.\n<li class=\"l\"> Suport pentru extensia RISC-V Zicond cu implementarea opera\u021biunilor condi\u021bionale.\n<li class=\"l\"> A fost integrat managementul frecven\u021bei de clock (clock gating).\n<li class=\"l\"> A fost implementat suport pentru limbajul HIP (Heterogeneous Interface for Portability) prin cadrul chipStar, care traduce HIP \u00een SPIR-V.\n<li class=\"l\"> A fost asigurat\u0103 integrarea complet\u0103 cu simulatorul GEM5 \u0219i a fost ad\u0103ugat suport pentru simulatorul SimX pe arhitectura TLM (Transaction-Level Modeling).\n<li class=\"l\"> A fost ad\u0103ugat suport pentru uneltele Synopsys \u0219i Yosys pentru sintaza logic\u0103 \u00een produc\u021bia de cipuri, precum \u0219i suport pentru utilizarea bibliotecilor de componente standard ASAP7 (7nm), SAED14 (14nm) \u0219i NanGate (15nm).\n<li class=\"l\"> Setul de unelte de referin\u021b\u0103 a fost actualizat la LLVM 20 \u0219i POCL 7.0.\n<\/ul>\n<p>Sursa: <a content=\"nofollow\" rel=\"nofollow\" href=\"https:\/\/www.opennet.ru\/opennews\/art.shtml?num=65652\">opennet.ro<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"<p>\u0414\u043e\u0441\u0442\u0443\u043f\u0435\u043d \u0432\u044b\u043f\u0443\u0441\u043a \u043f\u0440\u043e\u0435\u043a\u0442\u0430 Vortex 3.0, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0439 GPGPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V, \u0440\u0430\u0441\u0441\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0439 \u043d\u0430 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u0435 \u043f\u0430\u0440\u0430\u043b\u043b\u0435\u043b\u044c\u043d\u044b\u0445 \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439 \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c API OpenCL \u0438 \u043c\u043e\u0434\u0435\u043b\u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f SIMT (Single Instruction, Multiple Threads). \u041f\u0440\u043e\u0435\u043a\u0442 \u0442\u0430\u043a\u0436\u0435 \u043c\u043e\u0436\u0435\u0442 \u0431\u044b\u0442\u044c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d \u043f\u0440\u0438 \u043f\u0440\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u0438 \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0439 \u0432 \u043e\u0431\u043b\u0430\u0441\u0442\u0438 3D-\u0433\u0440\u0430\u0444\u0438\u043a\u0438 \u0438 \u043f\u0440\u0438 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0435 \u043d\u043e\u0432\u044b\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440 GPU. \u0421\u0445\u0435\u043c\u044b, \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u0445 \u0431\u043b\u043e\u043a\u043e\u0432 \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 Verilog, [&hellip;]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":8,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-181998","post","type-post","status-publish","format-standard","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.2 - aioseo.com -->\n\t<meta name=\"description\" content=\"\u0414\u043e\u0441\u0442\u0443\u043f\u0435\u043d \u0432\u044b\u043f\u0443\u0441\u043a \u043f\u0440\u043e\u0435\u043a\u0442\u0430 Vortex 3.0, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0439 GPGPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V, 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