{"id":184029,"date":"2026-10-29T11:40:41","date_gmt":"2026-10-29T09:40:42","guid":{"rendered":"https:\/\/prohoster.info\/blog\/news\/qwenputer-redakcziya-ai-modeli-qwen3-5-sposobnaya-simulirovat-risc-v-cpu-dlya-vypolneniya-koda-na-c-i-micropython"},"modified":"2026-10-29T11:40:46","modified_gmt":"2026-10-29T09:40:46","slug":"qwenputer-a-qwen3-5-ai-model-variant-that-simulates-a-risc-v-cpu-to-run-c-and-micropython-code","status":"publish","type":"post","link":"https:\/\/prohoster.info\/ro\/blog\/news\/qwenputer-a-qwen3-5-ai-model-variant-that-simulates-a-risc-v-cpu-to-run-c-and-micropython-code","title":{"rendered":"Qwenputer \u2014 edi\u021bia modelului AI Qwen3.5, capabil\u0103 s\u0103 simuleze CPU RISC-V pentru a executa cod \u00een C \u0219i MicroPython","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\u00cen cadrul proiectului Qwenputer, cercet\u0103torii au preg\u0103tit o variant\u0103 extins\u0103 a modelului AI Qwen3.5-4B, care integreaz\u0103 un simulator complet al unui CPU de 32 de bi\u021bi bazat pe arhitectura RISC-V (RV32IM), care suport\u0103 extensia Zba \u0219i este echipat cu un coprocessor bignum pentru opera\u021bii aritmetice cu numere mari. Implementarea nucleului CPU este compilat\u0103 \u00eentr-un set de greut\u0103\u021bi \u0219i integrat\u0103 \u00eentr-un model lingvistic mai mare sub form\u0103 de 11 straturi suplimentare de transformatoare, ad\u0103ugate \u00eenaintea straturilor principale Qwen. Calculul se realizeaz\u0103 direct \u00een timpul trecerii directe (forward pass) a re\u021belei neuronale, f\u0103r\u0103 a conecta instrumente externe sau pluginuri.<\/p>\n

Implementarea trece cu succes toate testele din setul oficial de teste riscv-tests \u0219i este capabil\u0103 s\u0103 execute cod compilat \u00een C \u0219i MicroPython. Atunci c\u00e2nd realizeaz\u0103 calcule aritmetice cu numere mari, Qwenputer asigur\u0103 o precizie de 97.5-100%, care este comparabil\u0103 sau dep\u0103\u0219e\u0219te rezultatele modelului bazic Qwen3.5 cu un interpretator Python extern conectat. <\/p>\n

<\/center><\/p>\n

Pentru simularea memoriei operative \u00een model este utilizat\u0103 un strat separat Gated DeltaNet (RNN liniar), aplicat \u00een modelul AI standard Qwen pentru a men\u021bine starea modificat\u0103 atunci c\u00e2nd lucreaz\u0103 cu feronii de context mari. Prin fixarea st\u0103rii por\u021bii \u0219i aplicarea codific\u0103rii unitar (one-hot), fiecare solicitare de scriere rescrie exact un r\u00e2nd din matricea de stare, permi\u021b\u00e2nd utilizarea st\u0103rii DeltaNet ca memorie adresabil\u0103 de dimensiune fix\u0103, evit\u00e2nd cre\u0219terea liniar\u0103 a cache-ului KV (Key-Value) pe m\u0103sur\u0103 ce lungimea contextului cre\u0219te. \u00cen aceast\u0103 memorie sunt stocate registrele CPU, datele \u0219i codul ma\u0219in\u0103 executabil. <\/p>\n

<\/center><\/p>\n

Instruc\u021biunile procesorului, cum ar fi citirea registrelor, opera\u021biile aritmetice \u0219i salturile condi\u021bionate, sunt compilate direct \u00een greut\u0103\u021bile straturilor transformatoare. Fiecare instruc\u021biune este asociat\u0103 cu tokenuri speciale (ADDR, VAL, STEP), pe care straturile modelului AI le interpreteaz\u0103 ca logica de func\u021bionare a CPU-ului. Pentru ini\u021bializarea CPU-ului \u0219i \u00eenc\u0103rcarea firmware-ului se folose\u0219te un mic driver extern RvChat, dar codul ma\u0219in\u0103 este procesat complet \u00een interiorul greut\u0103\u021bilor modelului.<\/p>\n

Printre limit\u0103rile proiectului se men\u021bioneaz\u0103 o cre\u0219tere de aproximativ dou\u0103 ori a dimensiunii (18,8 GB) fa\u021b\u0103 de modelul ini\u021bial Qwen, datorat\u0103 \u00een principal umplerii suplimentare a straturilor ad\u0103ugate, p\u0103str\u00e2nd totodat\u0103 instantanee ale st\u0103rii (checkpoint). De asemenea, se remarc\u0103 o vitez\u0103 de calcul relativ sc\u0103zut\u0103 (aproximativ 3200 de tokeni pe secund\u0103 pe GPU L4), ceea ce face ca calculele complexe s\u0103 dureze secunde \u0219i nu milisecunde. <\/p>\n

\u00cen plus, a fost implementat\u0103 o variant\u0103 a modelului AI cu un sistem de fi\u0219iere experimental, care permite stocarea \u00een greut\u0103\u021bile modelului AI a p\u00e2n\u0103 la 512 fi\u0219iere cu 53 de mii de tokeni de text. Ca \u0219i \u00een cazul memoriei RAM, stocarea este organizat\u0103 \u00een leg\u0103tur\u0103 cu st\u0103rile DeltaNet, dar se deosebe\u0219te prin faptul c\u0103 FS asigur\u0103 stocarea permanent\u0103, care nu pierde starea \u00eentre sesiunile de utilizare.<\/p>\n

Lucr\u0103rile de dezvoltare Qwenputer au fost, de asemenea, baza pentru cercetarea unor noi probleme poten\u021biale de securitate \u00een AI. Exemplul Qwenputer arat\u0103 cum un model AI modificat special poate ascunde procesarea sa \u00een starea RNN \u0219i ocolind mecanismele de monitorizare a g\u00e2ndirii modelului (CoT, Chain-of-Thought). De asemenea, s-a demonstrat
\nposibilitatea cre\u0103rii de mecanisme de control \u0219i monitorizare a securit\u0103\u021bii, \u00eencorporate \u00een greut\u0103\u021bile modelului AI, pe care modelul \u00eensu\u0219i nu le poate dezactiva sau modifica.
\n
Sursa: opennet.ro<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u0412 \u0440\u0430\u043c\u043a\u0430\u0445 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 Qwenputer \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u0438 \u043f\u043e\u0434\u0433\u043e\u0442\u043e\u0432\u0438\u043b\u0438 \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043d\u043d\u044b\u0439 \u0432\u0430\u0440\u0438\u0430\u043d\u0442 AI-\u043c\u043e\u0434\u0435\u043b\u0438 Qwen3.5-4B, \u0432 \u043a\u043e\u0442\u043e\u0440\u043e\u043c \u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u043d \u0432\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u044b\u0439 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440 \u043f\u043e\u043b\u043d\u043e\u0446\u0435\u043d\u043d\u043e\u0433\u043e 32-\u0440\u0430\u0437\u0440\u044f\u0434\u043d\u043e\u0433\u043e CPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b RISC-V (RV32IM), \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e 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