{"id":56073,"date":"2020-02-04T00:00:00","date_gmt":"2020-02-03T21:00:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/blog_prohoster\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry"},"modified":"2020-02-18T14:04:16","modified_gmt":"2020-02-18T11:04:16","slug":"neizbezhnost-proniknoveniya-fpga-v-data-tsentry","status":"publish","type":"post","link":"https:\/\/prohoster.info\/ro\/blog\/administrirovanie\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry","title":{"rendered":"Inevitabilitatea penetra\u021biei FPGA \u00een centrele de date","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\"Inevitabilitatea
\nNu trebuie s\u0103 fii dezvoltator de cipuri pentru a programa pentru FPGA, la fel cum nu trebuie s\u0103 fii programator C++ pentru a scrie cod \u00een Java. Cu toate acestea, \u00een ambele cazuri, este probabil c\u0103 acest lucru ar fi util.<\/p>\n

Scopul comercializ\u0103rii ambelor tehnologii, Java \u0219i FPGA, este acela de a contrazice ultimul argument. Ve\u0219tile bune pentru FPGA sunt c\u0103, utiliz\u00e2nd niveluri adecvate de abstractizare \u0219i un set de instrumente, \u00een ultimii 35 de ani, de c\u00e2nd a fost inventat dispozitivul logic programabil, devine tot mai u\u0219or s\u0103 creezi algoritmi \u0219i fluxuri de date pentru FPGA \u00een loc de CPU, DSP, GPU sau orice alt\u0103 form\u0103 de ASIC specializat.<\/p>\n

Temporalitatea uimitoare a cre\u0103rii lor se manifest\u0103 tocmai atunci c\u00e2nd CPU-urile nu mai pot r\u0103m\u00e2ne singurul modul de calcul. a centrelor de date<\/a> pentru a \u00eendeplini numeroase sarcini \u2013 din cele mai diverse motive \u2013 FPGA-urile au atins eficien\u021ba lor, oferind vitez\u0103, laten\u021b\u0103 redus\u0103, capacit\u0103\u021bi de re\u021bea \u0219i memorie \u2013 capacit\u0103\u021bile computa\u021bionale diverse ale FPGA-urilor moderne SoC, care reprezint\u0103 aproape sisteme complete de calcul. Cu toate acestea, FPGA-urile se combin\u0103 bine \u0219i cu alte dispozitive \u00een sisteme hibride, \u0219i, \u00een opinia noastr\u0103, abia \u00ee\u0219i \u00eencep s\u0103-\u0219i g\u0103seasc\u0103 locul legitim \u00een ierarhia calculului.
\n<\/a><\/noindex>
\nPrin urmare, am organizat conferin\u021ba The Next FPGA Platform \u00een San Jose pe 22 ianuarie. Evident, unul dintre principalii furnizori de FPGA din lume \u0219i pionier \u00een acest domeniu este compania Xilinx. Ivo BolSense, vicepre\u0219edinte senior \u0219i CTO al Xilinx, a sus\u021binut o prezentare la conferin\u021b\u0103 \u0219i ne-a \u00eemp\u0103rt\u0103\u0219it g\u00e2ndurile sale de ast\u0103zi despre cum Xilinx ajut\u0103 la crearea de sisteme de calcul modificabile pentru centrele de date.<\/p>\n

Arhitec\u021bii de sisteme \u0219i programatorii au investit mult timp pentru a ajunge la un centru de date eterogen, \u00een care s\u0103 fie prezente resurse computa\u021bionale de diverse tipuri, care s\u0103 rezolve probleme de calcul, stocare \u0219i organizare a re\u021belelor. Aceasta pare a fi o necesitate, av\u00e2nd \u00een vedere c\u0103 urmarea legii lui Moore cu ajutorul diverselor CMOS devine din ce \u00een ce mai dificil\u0103. Deocamdat\u0103, limbajul nostru este \u00eenc\u0103 legat de CPU, \u0219i \u00eenc\u0103 mai discut\u0103m despre \u201eaccelera\u021bia aplica\u021biilor\u201d, av\u00e2nd \u00een vedere \u00eembun\u0103t\u0103\u021birea performan\u021bei programelor \u00een compara\u021bie cu ceea ce se poate realiza doar cu CPU-uri. \u00centr-o bun\u0103 zi, centrele de date vor evolua \u00een seturi de resurse de calcul, stocare de date \u0219i protocoale care le leag\u0103 \u00eempreun\u0103, iar ne vom \u00eentoarce la termeni precum \u201ecalcul\u201d \u0219i \u201eaplica\u021bii\u201d. Calculul hibrid va deveni la fel de normal ca serviciile \u201ecloud\u201d de ast\u0103zi, bazate pe tehnici obi\u0219nuite sau ma\u0219ini virtuale<\/a>, \u0219i \u00eentr-un oarecare moment vom folosi pur \u0219i simplu cuv\u00e2ntul \u201ecalcul\u201d pentru a descrie func\u021bionarea lor. \u00centr-o oarecare m\u0103sur\u0103 \u2013 \u0219i, probabil, sosirea acestei ere va fi activ influen\u021bat\u0103 de FPGA \u2013 ne vom \u00eentoarce s\u0103 denumim aceasta procesarea datelor.<\/p>\n

Pentru a integra FPGA \u00een centrele de date, va fi necesar\u0103 o schimbare de mentalitate. \u201eG\u00e2ndindu-ne la modalit\u0103\u021bi de accelerare a aplica\u021biilor de ast\u0103zi, trebuie s\u0103 ne \u00eentoarcem la fundamentele modului \u00een care acestea sunt executate, ce resurse sunt utilizate, la ce se duce timpul\u201d, explic\u0103 Boltzens. \u2013 Este necesar s\u0103 studiem problema general\u0103 pe care \u00eencerca\u021bi s\u0103 o rezolva\u021bi. Multe aplica\u021bii care opereaz\u0103 \u00een centrele de date de ast\u0103zi sunt scalabile, captur\u00e2nd un mare volum de resurse. S\u0103 lu\u0103m, de exemplu, \u00eenv\u0103\u021barea automat\u0103, care utilizeaz\u0103 un num\u0103r uria\u0219 de noduri de calcul. Dar atunci c\u00e2nd vorbim despre accelerare, trebuie s\u0103 ne g\u00e2ndim nu doar la accelerarea calculului, ci \u0219i la accelerarea infrastructurii.\u201d<\/p>\n

De exemplu, \u00een opera\u021biunile legate de \u00eenv\u0103\u021barea automat\u0103 pe care le-a studiat Boltzens \u00een practic\u0103, aproximativ 50% din timp este cheltuit pe transferul de date \u00een ambele direc\u021bii \u00eentre resursele de calcul dispersate, iar doar restul de jum\u0103tate din timp este dedicat efectiv calculului.<\/p>\n

Cred c\u0103 aici FPGA poate aduce un real ajutor, deoarece putem optimiza at\u00e2t aspectele de calcul, c\u00e2t \u0219i cele de transfer de date pentru aplica\u021bie. Putem face acest lucru at\u00e2t la nivelul infrastructurii generale, c\u00e2t \u0219i la nivelul cipului. Aceasta este una dintre marile avantaje ale FPGA, permi\u021b\u00e2nd crearea de re\u021bele de comunica\u021bie adaptate nevoilor specifice ale aplica\u021biei. Observ\u00e2nd tiparele tipice de mi\u0219care a datelor \u00een sarcini legate de inteligen\u021ba artificial\u0103, nu v\u0103d necesitatea unei arhitecturi complexe bazate pe comutatoare. Se poate construi o re\u021bea cu un volum mare de date. Acela\u0219i lucru este valabil \u0219i pentru sarcinile de \u00eenv\u0103\u021bare a re\u021belelor neuronale \u2013 se poate construi o re\u021bea celular\u0103 cu dimensiuni ale pachetelor adaptate la sarcina specific\u0103. Folosind FPGA, se pot scala \u0219i adapta cu precizie protocoalele de transfer de date \u0219i topologia circuitului pentru aplica\u021bia specific\u0103. \u0218i \u00een cazul \u00eenv\u0103\u021b\u0103rii automate, este de asemenea evident c\u0103 nu avem nevoie de numere \u00een virgul\u0103 mobil\u0103 de precizie dubl\u0103, iar aceasta poate fi adaptat\u0103 \u0219i ea.<\/p>\n

Diferen\u021ba dintre FPGA \u0219i CPU sau ASIC-uri specializate este c\u0103 ultimele sunt programate \u00een timpul produc\u021biei, iar dup\u0103 aceea nu mai po\u021bi r\u0103zg\u00e2ndi tipurile de date calculate sau elementele calculate, sau natura fluxului de date care trece prin dispozitiv. FPGA-urile \u00ee\u021bi permit s\u0103 te r\u0103zg\u00e2nde\u0219ti dac\u0103 condi\u021biile de operare se schimb\u0103.<\/p>\n

\u00cen trecut, acest avantaj era costisitor, c\u00e2nd programarea pentru FPGA era destinat\u0103 doar celor puternici. Este necesar s\u0103 deschizi compilatoarele pentru FPGA, astfel \u00eenc\u00e2t acestea s\u0103 se integreze mai bine cu instrumentele utilizate de programatori pentru a crea aplica\u021bii cu calcul paralel pentru CPU \u00een limbaje precum C, C++ sau Python, \u0219i s\u0103 delegi parte din munc\u0103 bibliotecilor care accelereaz\u0103 procedurile pe FPGA. Aceasta este ceea ce face stack-ul pentru \u00eenv\u0103\u021barea automat\u0103 Vitis, care st\u0103 la baza unor platforme pentru MA, precum Caffe \u0219i TensorFlow, \u0219i are biblioteci pentru a rula modelele AI obi\u0219nuite sau pentru a ad\u0103uga capacit\u0103\u021bi FPGA la sarcini precum transcodarea video, recunoa\u0219terea obiectelor \u00een video, analiza datelor, gestionarea riscurilor financiare \u0219i orice biblioteci externe.<\/p>\n

Aceast\u0103 conceptie nu se deosebe\u0219te prea mult de proiectul CUDA de la Nvidia, lansat acum zece ani, care a delegat calculul paralel pe acceleratoarele GPU, sau de setul de instrumente ROCm de la AMD, sau de promisiunile proiectului Intel, OneAPI, care ar trebui s\u0103 func\u021bioneze pe diferite CPU, GPU \u0219i FPGA.<\/p>\n

\u00centrebarea este doar cum toate aceste instrumente vor fi corelate astfel \u00eenc\u00e2t oricine s\u0103 poat\u0103 programa un set de capacit\u0103\u021bi de calcul dup\u0103 bunul plac. Acest lucru este important deoarece FPGA-urile au devenit mai complicate, mult mai complicate dec\u00e2t oricare dintre CPU-urile existente. Ele sunt fabricate cu cele mai avansate procese tehnologice \u0219i utiliz\u00e2nd cele mai moderne tehnologii de ambalare a chipurilor. \u0218i \u00ee\u0219i vor g\u0103si ni\u0219a, deoarece nu mai putem pierde timp, bani, energie \u0219i inteligen\u021b\u0103 \u2013 toate acestea fiind resurse prea costisitoare.<\/p>\n

\u201eFPGA ofer\u0103 avantaje tehnologice\u201d, spune Bolsens. \u201e\u0218i nu este doar o reclam\u0103 obi\u0219nuit\u0103 despre adaptabilitate \u0219i reconfigurabilitate. \u00cen toate aplica\u021biile importante \u2013 \u00eenv\u0103\u021bare automat\u0103, analiz\u0103 de grafuri, trading de \u00eenalt\u0103 vitez\u0103 etc. \u2013 au capacitatea de a adapta nu doar calea de propagare a datelor, ci \u0219i arhitectura memoriei \u2013 modul \u00een care datele se mut\u0103 \u00een cadrul chipului. De asemenea, FPGA-urile au mult mai mult\u0103 memorie integrat\u0103 dec\u00e2t alte dispozitive. Trebuie, de asemenea, s\u0103 lu\u0103m \u00een considerare c\u0103, dac\u0103 sarcina nu \u00eencap\u0103 \u00eentr-un singur FPGA, aceasta poate fi scalat\u0103 pe mai multe chipuri, f\u0103r\u0103 a \u00eent\u00e2mpina acele dezavantaje care v\u0103 a\u0219teapt\u0103 atunci c\u00e2nd scalati sarcinile pe mai multe CPU-uri sau GPU-uri.\u201d
\n
Sursa: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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