{"id":84726,"date":"2020-06-10T13:42:19","date_gmt":"2020-06-10T11:42:19","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v"},"modified":"2020-06-10T13:42:19","modified_gmt":"2020-06-10T11:42:19","slug":"mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/ro\/blog\/news\/mikroyadro-sel4-matematicheski-verificzirovano-dlya-arhitektury-risc-v","title":{"rendered":"Microkernelul seL4 a fost verificat matematic pentru arhitectura RISC-V","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Organiza\u021bia RISC-V Foundation a declarat<\/a><\/noindex> despre verificarea func\u021bion\u0103rii microkernel-ului seL4<\/a><\/noindex> pe sisteme cu arhitecturi de seturi de instruc\u021biuni RISC-V. Verificarea se reduce la o dovad\u0103 matematic\u0103<\/a><\/noindex> a fiabilit\u0103\u021bii func\u021bion\u0103rii seL4, care atest\u0103 conformitatea complet\u0103 cu specifica\u021biile definite \u00eentr-un limbaj formal. Dovada fiabilit\u0103\u021bii permite utilizarea<\/a><\/noindex> seL4 \u00een sisteme critice bazate pe procesoare RISC-V RV64, care necesit\u0103 un nivel ridicat de fiabilitate \u0219i garantarea absen\u021bei erorilor. Dezvoltatorii de software care ruleaz\u0103 pe kernel-ul seL4 pot fi complet \u00eencrez\u0103tori c\u0103, \u00een cazul unei erori \u00eentr-o parte a sistemului, acea eroare nu se va r\u0103sp\u00e2ndi \u00een restul sistemului \u0219i, \u00een special, \u00een p\u0103r\u021bile sale critice. <\/p>\n

Ini\u021bial, microkernel-ul seL4 a fost verificat pentru procesoare ARM pe 32 de bi\u021bi, iar ulterior pentru procesoare x86 pe 64 de bi\u021bi. Se remarc\u0103 faptul c\u0103 combina\u021bia \u00eentre arhitectura hardware deschis\u0103 RISC-V \u0219i microkernel-ul deschis seL4 va permite atingerea unui nou nivel de securitate, deoarece componentele hardware ar putea fi de asemenea complet verificate \u00een viitor, ceea ce nu este posibil pentru arhitecturile hardware proprietare. <\/p>\n

\u00cen timpul verific\u0103rii seL4, se presupune c\u0103 hardware-ul func\u021bioneaz\u0103 conform specifica\u021biilor \u0219i c\u0103 documenta\u021bia descrie complet comportamentul sistemului. Totu\u0219i, \u00een practic\u0103, hardware-ul nu este lipsit de erori, ceea ce este bine ilustrat de problemele frecvente ap\u0103rute \u00een mecanismul de execu\u021bie speculativ\u0103 a instruc\u021biunilor. Platformele hardware deschise simplific\u0103 integrarea modific\u0103rilor legate de securitate - de exemplu, pentru a bloca toate canalele posibile de scurgere prin canale externe, unde este mult mai eficient s\u0103 rezolvi problema la nivel de hardware dec\u00e2t s\u0103 cau\u021bi solu\u021bii software.<\/p>\n

Reamintim c\u0103 arhitectura seL4 este deosebit\u0103<\/a><\/noindex> \u00eendep\u0103rtarea p\u0103r\u021bilor pentru gestionarea resurselor nucleului \u00een spa\u021biul utilizatorului \u0219i aplicarea pentru astfel de resurse a acelora\u0219i instrumente de delimitare a accesului ca pentru resursele utilizatorului. Microkernelul nu ofer\u0103 abera\u021bii de nivel \u00eenalt predefinite pentru gestionarea fi\u0219ierelor, proceselor, conexiunilor de re\u021bea etc., ci ofer\u0103 doar mecanisme minime pentru gestionarea accesului la spa\u021biul fizic de adresare, \u00eentreruperi \u0219i resursele procesorului. Abstrac\u021biile de nivel \u00eenalt \u0219i driverele pentru interac\u021biunea cu hardware-ul sunt implementate separat deasupra microkernelului sub form\u0103 de sarcini executate la nivelul utilizatorului. Accesul acestor sarcini la resursele disponibile ale microkernelului este organizat prin definirea regulilor.<\/p>\n

RISC-V ofer\u0103 un sistem deschis \u0219i flexibil de instruc\u021biuni ma\u0219in\u0103, permi\u021b\u00e2nd crearea de microprocesoare pentru domenii de aplica\u021bie diverse, f\u0103r\u0103 a necesita redeven\u021be \u0219i f\u0103r\u0103 a impune condi\u021bii de utilizare. RISC-V permite crearea de SoC-uri \u0219i procesoare complet deschise. \u00cen prezent, diverse companii \u0219i comunit\u0103\u021bi dezvolt\u0103, baz\u00e2ndu-se pe specifica\u021bia RISC-V, o serie de produse sub diverse licen\u021be libere (BSD, MIT, Apache 2.0). se dezvolt\u0103<\/a><\/noindex> c\u00e2teva zeci de variante de nuclee de microprocesoare, SoC-uri \u0219i cipuri deja fabricate. Suportul pentru RISC-V este disponibil \u00eencep\u00e2nd cu versiunile Glibc 2.27, binutils 2.30, gcc 7 \u0219i nucleul Linux 4.15.<\/p>\n

<\/a><\/noindex><\/p>\n

Sursa: opennet.ro<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041e\u0440\u0433\u0430\u043d\u0438\u0437\u0430\u0446\u0438\u044f RISC-V Foundation \u0441\u043e\u043e\u0431\u0449\u0438\u043b\u0430 \u043e \u0432\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u0438 \u0440\u0430\u0431\u043e\u0442\u044b \u043c\u0438\u043a\u0440\u043e\u044f\u0434\u0440\u0430 seL4 \u043d\u0430 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u0445 \u0441 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043e\u0439 \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V. \u0412\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f \u0441\u0432\u043e\u0434\u0438\u0442\u0441\u044f \u043a \u043c\u0430\u0442\u0435\u043c\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u043e\u043c\u0443 \u0434\u043e\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u0443 \u043d\u0430\u0434\u0451\u0436\u043d\u043e\u0441\u0442\u0438 \u0440\u0430\u0431\u043e\u0442\u044b seL4, \u043a\u043e\u0442\u043e\u0440\u043e\u0435 \u0441\u0432\u0438\u0434\u0435\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u0443\u0435\u0442 \u043e \u043f\u043e\u043b\u043d\u043e\u043c \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0438\u0438 \u0437\u0430\u0434\u0430\u043d\u043d\u044b\u043c \u043d\u0430 \u0444\u043e\u0440\u043c\u0430\u043b\u044c\u043d\u043e\u043c \u044f\u0437\u044b\u043a\u0435 \u0441\u043f\u0435\u0446\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f\u043c. \u0414\u043e\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044c\u0441\u0442\u0432\u043e \u043d\u0430\u0434\u0451\u0436\u043d\u043e\u0441\u0442\u0438 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c seL4 \u0432 \u043a\u0440\u0438\u0442\u0438\u0447\u0435\u0441\u043a\u0438 \u0432\u0430\u0436\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u0445 \u043d\u0430 \u0431\u0430\u0437\u0435 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 RISC-V RV64, \u0442\u0440\u0435\u0431\u0443\u044e\u0449\u0438\u0445 \u043f\u043e\u0432\u044b\u0448\u0435\u043d\u043d\u043e\u0433\u043e \u0443\u0440\u043e\u0432\u043d\u044f \u043d\u0430\u0434\u0451\u0436\u043d\u043e\u0441\u0442\u0438 \u0438 \u0433\u0430\u0440\u0430\u043d\u0442\u0438\u0440\u0443\u044e\u0449\u0438\u0445 \u043e\u0442\u0441\u0443\u0442\u0441\u0442\u0432\u0438\u0435 […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-84726","post","type-post","status-publish","format-standard","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Microkernelul seL4 a fost verificat matematic pentru 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