{"id":30031,"date":"2019-10-31T21:33:20","date_gmt":"2019-10-31T18:33:20","guid":{"rendered":"https:\/\/prohoster.info\/blog\/linux-foundation-zajmetsya-open-source-chipami\/"},"modified":"2019-10-31T21:33:20","modified_gmt":"2019-10-31T18:33:20","slug":"linux-foundation-zajmetsya-open-source-chipami","status":"publish","type":"post","link":"https:\/\/prohoster.info\/sk\/blog\/linux-foundation-zajmetsya-open-source-chipami","title":{"rendered":"Linux Foundation sa bude zaobera\u0165 open source \u010dipmi","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Linux Foundation otvorili nov\u00fd smer \u2014 CHIPS Alliance. V r\u00e1mci tohto projektu organiz\u00e1cia bude rozv\u00edja\u0165 otvoren\u00fd syst\u00e9m RISC-V a technol\u00f3gie na vytv\u00e1ranie procesorov na jeho z\u00e1klade. Povieme si podrobnej\u0161ie, \u010do sa v tejto oblasti deje.<\/p>\n

\"Linux<\/a><\/noindex><\/a><\/noindex>
\n\/ \u0444\u043e\u0442\u043e Gareth Halfacree<\/a><\/noindex> CC BY-SA<\/a><\/noindex><\/i><\/p>\n

Pre\u010do vznikla CHIPS Alliance<\/h2>\n

\nZ\u00e1platy, ktor\u00e9 chr\u00e1nia pred Meltdown a Spectre, v niektor\u00fdch pr\u00edpadoch zni\u017euj\u00fa v\u00fdkon<\/a><\/noindex> serverov o 50%. Napriek tomu sa na\u010falej objavuj\u00fa nov\u00e9 vari\u00e1cie zranite\u013enost\u00ed spojen\u00e9 so spekulat\u00edvnym vykon\u00e1van\u00edm pr\u00edkazov. O jednej z nich sa dozvedelo za\u010diatkom marca<\/a><\/noindex> \u2014 odborn\u00edci na IT bezpe\u010dnos\u0165 ozna\u010dili ju za Spoiler. T\u00e1to situ\u00e1cia ovplyv\u0148uje diskusiu<\/a><\/noindex> o potrebe rev\u00edzie existuj\u00facich hardv\u00e9rov\u00fdch rie\u0161en\u00ed a pr\u00edstupov k ich v\u00fdvoju. Konkr\u00e9tne, Intel u\u017e pripravuje<\/a><\/noindex> nov\u00fa architekt\u00faru svojich procesorov, ktor\u00e1 nie je n\u00e1chyln\u00e1 na Meltdown a Spectre.<\/p>\n

Nenechali sa stranou ani v Linux Foundation. Organiz\u00e1cia spustila vlastn\u00fa iniciat\u00edvu \u2014 CHIPS Alliance \u2014 ktor\u00fdch \u00fa\u010dastn\u00edci sa bud\u00fa zaobera\u0165 rozvojom procesorov na b\u00e1ze RISC-V.<\/p>\n

Ak\u00e9 projekty u\u017e vyv\u00edjaj\u00fa<\/h2>\n

<\/p>\n

Na zozname \u00fa\u010dastn\u00edkov CHIPS Alliance s\u00fa Google, Western Digital (WD) a SiFive. Ka\u017ed\u00e1 z nich predstavila svoje vlastn\u00e9 v\u00fdvojov\u00e9 projekty. Povieme si o niektor\u00fdch z nich.<\/p><\/blockquote>\n

<\/p>\n

RISCV-DV<\/h5>\n

\nVyh\u013ead\u00e1vac\u00ed IT gigant prekonal open source platformu pre testovanie procesorov na b\u00e1ze RISC-V. Rie\u0161enie n\u00e1hodne generuje<\/a><\/noindex> pr\u00edkazy, ktor\u00e9 umo\u017e\u0148uj\u00fa<\/a><\/noindex> overuj\u00fa funk\u010dnos\u0165 zariadenia: testuj\u00fa procesy prechodu, z\u00e1sobn\u00edka volan\u00ed, CSR<\/a><\/noindex>-registre a \u010fal\u0161ie.<\/p>\n

Napr\u00edklad, takto vyzer\u00e1 trieda<\/a><\/noindex>, ktor\u00e1 je zodpovedn\u00e1 za vykon\u00e1vanie jednoduch\u00e9ho testu aritmetick\u00fdch in\u0161trukci\u00ed:<\/p>\n

class riscv_arithmetic_basic_test extends riscv_instr_base_test;\n\n  `uvm_component_utils(riscv_arithmetic_basic_test)\n  `uvm_component_new\n\n  virtual function void randomize_cfg();\n    cfg.instr_cnt = 10000;\n    cfg.num_of_sub_program = 0;\n    cfg.no_fence = 1;\n    cfg.no_data_page = 1'b1;\n    cfg.no_branch_jump = 1'b1;\n    `DV_CHECK_RANDOMIZE_WITH_FATAL(cfg,\n                                   init_privileged_mode == MACHINE_MODE;\n                                   max_nested_loop == 0;)\n    `uvm_info(`gfn, $sformatf(\"riscv_instr_gen_config is randomized:n%0s\",\n                    cfg.sprint()), UVM_LOW)\n  endfunction\n\nendclass\n<\/code><\/pre>\n
\nV porovnan\u00ed s\u00fahrnu<\/a><\/noindex> v\u00fdvoj\u00e1rov, platforma sa od svojich n\u00e1protivkov l\u00ed\u0161i t\u00fdm, \u017ee umo\u017e\u0148uje postupne overi\u0165 v\u0161etky komponenty \u010dipu, vr\u00e1tane pam\u00e4\u0165ov\u00e9ho bloku.<\/p>\n
Protokol OmniXtend<\/h5>\n
\nTo je sie\u0165ov\u00fd protokol od WD, ktor\u00fd zabezpe\u010duje koherenciu cache pri prenose d\u00e1t cez Ethernet. OmniXtend<\/a><\/noindex> umo\u017e\u0148uje p\u0159\u00edmou v\u00fdm\u011bnu zpr\u00e1v s cache procesoru a pou\u017e\u00edv\u00e1 se k p\u0159ipojen\u00ed r\u016fzn\u00fdch akceler\u00e1tor\u016f: GPU nebo FPGA. Tak\u00e9 je vhodn\u00fd pro vytv\u00e1\u0159en\u00ed syst\u00e9m\u016f zalo\u017een\u00fdch na v\u00edce \u010dipech RISC-V.<\/p>\n
Protokol je ji\u017e podporov\u00e1n \u010dipy SweRV<\/a><\/noindex>, zam\u011b\u0159en\u00fdmi na zpracov\u00e1n\u00ed dat v datov\u00fdch centrech. SweRV je 32bitov\u00fd dvoucestn\u00fd superskal\u00e1rn\u00ed procesor vyroben\u00fd pomoc\u00ed 28nm technologie. Ka\u017ed\u00e1 cesta m\u00e1 dev\u011bt \u00farovn\u00ed, co\u017e umo\u017e\u0148uje na\u010d\u00edt\u00e1n\u00ed a prov\u00e1d\u011bn\u00ed n\u011bkolika povel\u016f sou\u010dasn\u011b. Za\u0159\u00edzen\u00ed pracuje na frekvenci 1,8 GHz.<\/p>\n
Gener\u00e1tor Rocket Chip<\/h5>\n
\n\u0158e\u0161en\u00ed od spole\u010dnosti SiFive, kterou zalo\u017eili v\u00fdvoj\u00e1\u0159i technologie RISC-V. Rocket Chip<\/a><\/noindex> je gener\u00e1tor procesorov\u00fdch jader RISC-V napsan\u00fd v jazyce Chisel. Je predstavuje<\/a><\/noindex> sada parametrizovan\u00fdch knihoven, kter\u00e9 se pou\u017e\u00edvaj\u00ed k vytv\u00e1\u0159en\u00ed SoC<\/a><\/noindex>.<\/p>\n
\u010co sa t\u00fdka Chisel<\/a><\/noindex>, to je jazyk popisu hardwaru zalo\u017een\u00fd na Scale. Generuje n\u00edzko\u00farov\u0148ov\u00fd k\u00f3d ve Verilogu, kter\u00fd je vhodn\u00fd<\/a><\/noindex> pro zpracov\u00e1n\u00ed na ASIC a FPGA. Takto umo\u017e\u0148uje vyu\u017e\u00edvat principy OOP p\u0159i v\u00fdvoji RTL<\/a><\/noindex>.<\/p>\n
Vyhl\u00eddky aliance<\/h2>\n
\nOdborn\u00edci tvrd\u00ed, \u017ee iniciativa Linux Foundation u\u010din\u00ed trh procesor\u016f demokrati\u010dt\u011bj\u0161\u00edm a otev\u0159en\u011bj\u0161\u00edm pro nov\u00e9 hr\u00e1\u010de. V IDC poznamen\u00e1vaj\u00fa<\/a><\/noindex>, \u017ee rostouc\u00ed popularita takov\u00fdch projekt\u016f pozitivn\u011b ovlivn\u00ed v\u00fdvoj technologi\u00ed strojov\u00e9ho u\u010den\u00ed a syst\u00e9m\u016f AI celkov\u011b.<\/p>\n
\"Linux
\n\/ \u0444\u043e\u0442\u043e Fritzchens Fritz<\/a><\/noindex> PD<\/i><\/p>\n
Rozvoj open source procesor\u016f tak\u00e9 povede ke sn\u00ed\u017een\u00ed n\u00e1klad\u016f na n\u00e1vrh vlastn\u00edch \u010dip\u016f. To se v\u0161ak stane pouze v p\u0159\u00edpad\u011b, \u017ee komunit\u011b Linux Foundation se poda\u0159\u00ed p\u0159il\u00e1kat dostate\u010dn\u00fd po\u010det v\u00fdvoj\u00e1\u0159\u016f.<\/p>\n
Podobn\u00e9 projekty<\/h2>\n
\nN\u00e1vrhem projekt\u016f, spojen\u00fdch s otev\u0159en\u00fdm hardwarem, se zab\u00fdvaj\u00ed i jin\u00e9 organizace. P\u0159\u00edkladem m\u016f\u017ee b\u00fdt konsorcium CXL, kter\u00e9 v polovin\u011b b\u0159ezna p\u0159edstavilo standard Compute Express Link. Technologie je analogem OmniXtend a tak\u00e9 spojuje CPU, GPU, FPGA. Pro v\u00fdm\u011bnu dat standard pou\u017e\u00edv\u00e1 sb\u011brnici PCIe 5.0.<\/p>\n
Dal\u0161\u00edm projektem, kter\u00fd se zab\u00fdv\u00e1 v\u00fdvojem procesorov\u00fdch technologi\u00ed, je MIPS Open, kter\u00fd vznikl v prosinci 2018. Iniciativu zalo\u017eil startup Wave Computing. V\u00fdvoj\u00e1\u0159i pl\u00e1nuj\u00ed otev\u0159\u00edt<\/a><\/noindex> IT komunit\u011b p\u0159\u00edstup k posledn\u00edm 32- a 64bitov\u00fdm instruk\u010dn\u00edm sad\u00e1m MIPS. Start projektu o\u010dak\u00e1va sa<\/a><\/noindex> v nejbli\u017e\u0161\u00edch m\u011bs\u00edc\u00edch.<\/p>\n
V\u0161eobecne sa pr\u00edstup open source st\u00e1va be\u017en\u00fdm nielen pre softv\u00e9r, ale aj pre hardv\u00e9r. Tak\u00e9to projekty podporuj\u00fa ve\u013ek\u00e9 spolo\u010dnosti. Preto m\u00f4\u017eeme o\u010dak\u00e1va\u0165, \u017ee u\u017e v bl\u00edzkej bud\u00facnosti sa na trhu objav\u00ed viac zariaden\u00ed zalo\u017een\u00fdch na otvoren\u00fdch hardv\u00e9rov\u00fdch \u0161tandardoch.<\/p>\n
\nNajnov\u0161ie pr\u00edspevky z n\u00e1\u0161ho firemn\u00e9ho blogu:<\/p>\n