{"id":33621,"date":"2019-10-31T21:53:47","date_gmt":"2019-10-31T18:53:47","guid":{"rendered":"https:\/\/prohoster.info\/blog\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620\/"},"modified":"2019-10-31T21:53:47","modified_gmt":"2019-10-31T18:53:47","slug":"additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","status":"publish","type":"post","link":"https:\/\/prohoster.info\/sl\/blog\/administrirovanie\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","title":{"rendered":"Dodatni uplinki v arhitekturi sistemske logike Intel C620","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Na x86 arhitekturi obstajata dva medsebojno dopolnjujo\u010da se pristopa. Po enem je treba stremeti k integraciji ra\u010dunalni\u0161kih in upravljalskih virov v en sam kristal. Drugi pristop poudarja razporeditev nalog: procesor je opremljen z zmogljivo zbirno napravo, ki oblikuje periferno raz\u0161irljivo ekosistemo. Ta koncept je osnova za topologijo sistemske logike Intel C620 za visoko zmogljive platforme.<\/a><\/noindex><\/p>\n

Klju\u010dna razlika v primerjavi s prej\u0161njim \u010dipsetom Intel C610 je raz\u0161iritev komunikacijskega kanala procesorja s perifernimi napravami, vklju\u010denimi v mikrokontroler PCH, z uporabo PCIe povezav poleg tradicionalne DMI zbirne naprave.<\/p>\n

\"Dodatni
\n
\nPodrobneje razmislimo o novostih ju\u017enega mostu Intel Lewisburg: kak\u0161ne evolucijske in revolucionarne pristope je uporabil za raz\u0161iritev svojih pooblastil v komunikaciji s procesorji?<\/p>\n

Evolucijske spremembe v komunikaciji CPU-PCH<\/h2>\n

\nV okviru evolucijskega pristopa je glavni komunikacijski kanal CPU in ju\u017enega mostu, ki je zbirna naprava DMI (Direct Media Interface), prejel podporo za re\u017eim PCIe x4 Gen3 z zmogljivostjo 8.0 GT\/S. Prej, pri Intel C610 PCH, je bila komunikacija procesorja in sistemske logike izvedena v re\u017eimu PCIe x4 Gen 2 z pasovno \u0161irino 5.0 GT\/S.<\/p>\n

\"Dodatni
\n
\nPrimerjava funkcionalnosti sistemske logike Intel C610 in C620<\/em><\/p>\n

Opazimo, da je ta podsklop znatno bolj konzervativen v primerjavi z vgrajenimi PCIe vrati procesorja, ki se obi\u010dajno uporabljajo za priklju\u010ditev GPU in NVMe pomnilnikov, kjer se \u017ee dolgo uporablja PCIe 3.0 in se pripravlja prehod na PCI Express Gen4.<\/p>\n

Revolucionarne spremembe v komunikaciji CPU-PCH<\/h2>\n

\nK revolucionarnim spremembam lahko \u0161tejemo dodajanje novih PCIe komunikacijskih kanalov CPU-PCH, imenovanih Additional Uplinks. Fizi\u010dno gre za dva PCI Express priklju\u010dka, ki delujeta v re\u017eimih PCIe x8 Gen3 in PCIe x16 Gen3, oba z 8.0 GT\/S.<\/p>\n

\"Dodatni
\n
\nZa interakcijo med CPU in Intel C620 PCH se uporabljajo 3 zbirne naprave: DMI in dva PCI Express priklju\u010dka.<\/em><\/p>\n

Zakaj je bilo potrebno ponovno preu\u010diti obstoje\u010do topologijo komunikacije z Intel C620? Prvi\u010d, v okviru PCH je lahko integrirano do 4x 10GbE omre\u017enih krmilnikov z funkcionalnostjo RDMA. Drugi\u010d, za \u0161ifriranje omre\u017enega prometa in izmenjavo z pomnilni\u0161ko podsklopom je odgovoren nov in hitrej\u0161i nabor soprocesorjev Intel QuickAssist Technology (QAT), ki zagotavljajo strojno podporo za stiskanje in \u0161ifriranje. In nenazadnje, \"motor inovacij\" \u2014 Innovation Engine<\/a><\/noindex>, ki bo na voljo samo OEM proizvajalcem.<\/p>\n

Prilagodljivost in fleksibilnost<\/h2>\n

\nPomembna lastnost je mo\u017enost prostovoljnega izbora ne le topologije povezave PCH, ampak tudi prioritet notranjih virov \u010dipa pri dostopu do hitrih komunikacijskih kanalov s procesorjem (procesorji). Poleg tega se v posebnem na\u010dinu EPO (EndPoint Only Mode) povezava PCH vzpostavi v statusu obi\u010dajne naprave PCI Express, ki vsebuje vire 10 GbE in Intel QAT. Pri tem sta klasi\u010dni vmesnik DMI in nekateri dedi\u0161\u010dinski podsistemi, prikazani na diagramu s \u010drno barvo, onemogo\u010dena.<\/p>\n

\"Dodatni
\n
\nNotranja arhitektura \u010dipa Intel C620 PCH<\/em><\/p>\n

Teoreti\u010dno to omogo\u010da uporabo ve\u010d kot enega \u010dipa Intel C620 PCH v sistemu, kar pove\u010duje funkcionalnost 10 GbE in Intel QAT v skladu z zahtevami po zmogljivosti. Pri tem so dedi\u0161\u010dinske funkcije, potrebne le v enem samem primeru, lahko vklju\u010dene le pri enem od name\u0161\u010denih \u010dipov PCH.<\/p>\n

Tako bo kon\u010dna beseda pri oblikovanju pripadala razvijalcu platforme, ki deluje na podlagi tako tehnolo\u0161kih kot tr\u017enih dejavnikov v skladu s pozicioniranjem vsakega konkretnega izdelka.
\n
Izvor: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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Po eni razli\u010dici, je potrebno iti v smeri integracije ra\u010dunskih in upravljalskih virov v eni kristalni strukturi.","canonical_url":"https:\/\/prohoster.info\/sl\/blog\/administrirovanie\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","robots":"max-image-preview:large","keywords":"","webmasterTools":{"miscellaneous":""},"schema":null,"og:locale":"sl_SI","og:site_name":"ProHoster | \u041a\u0443\u043f\u0438\u0442\u044c \u043d\u0430\u0434\u0435\u0436\u043d\u044b\u0439 \u0445\u043e\u0441\u0442\u0438\u043d\u0433 \u0434\u043b\u044f \u0441\u0430\u0439\u0442\u043e\u0432 \u0441 \u0437\u0430\u0449\u0438\u0442\u043e\u0439 \u043e\u0442 DDoS, VPS VDS \u0441\u0435\u0440\u0432\u0435\u0440\u044b","og:type":"article","og:title":"\ud83e\udd47Additional Uplinks \u0432 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0435 \u0441\u0438\u0441\u0442\u0435\u043c\u043d\u043e\u0439 \u043b\u043e\u0433\u0438\u043a\u0438 Intel C620 | ProHoster","og:description":"\u0412 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